Inventor

KUMAR SAILESH

US90 patents

⚠️ This page may combine multiple inventors who share the name “KUMAR SAILESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUMAR SAILESH

Netspeed Systems

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Asymmetric mesh NoC topologies

System and method for visualization of NoC performance based on simulation output

Asymmetric mesh NoC topologies

Hardware and software enabled implementation of power profile management instructions in system on chip

Configurable router for a network on chip (NoC)

Streaming bridge design with host interfaces and network on chip (NoC) layers

Supporting multicast in NoC interconnect

Integrated NoC for performing data communication and NoC functions

Congestion control and QoS in NoC by regulating the injection traffic

Automatic pipelining of NoC channels to meet timing and/or performance

Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements

Supporting multicast in NOC interconnect

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Transactional traffic specification for network-on-chip design

Integrated NoC for performing data communication and NoC functions

Using multiple traffic profiles to design a network on chip

Combining associativity and cuckoo hashing

Automatic buffer sizing for optimal network-on-chip design

Clock gating for system-on-chip elements

Using cuckoo movement for improved cache coherency

Specification for automatic power management of network-on-chip and system-on-chip

System level simulation in network on chip architecture

System and method for improving snoop performance

Heterogeneous channel capacities in an interconnect

Asymmetric mesh NoC topologies

Multiple clock domains in NoC

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

System level simulation in Network on Chip architecture

Automatic generation of power management sequence in a SoC or NoC

Automatic NoC topology generation

Automatic performance characterization of a network-on-chip (NOC) interconnect

Generation of network-on-chip layout based on user specified topological constraints

Automatic generation of physically aware aggregation/distribution networks

Automatic pipelining of NoC channels to meet timing and/or performance

Automatic generation of power management sequence in a SoC or NoC

NETSPEED SYSTEMS INC

System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology

Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)

Systems and methods for facilitating low power on a network-on-chip

Automatic buffer sizing for optimal network-on-chip design

System on chip (SoC) builder

Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation

Extracting features from a NoC for machine learning construction

Buffer sizing of a NoC through machine learning

KUMAR SAILESH

Hierarchical asymmetric mesh with virtual routers

Multiple heterogeneous NoC layers

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

PHILIP JOJI

Automatic construction of deadlock free interconnects