Inventor

NORIGE ERIC

US39 patents

⚠️ This page may combine multiple inventors who share the name “NORIGE ERIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NORIGE ERIC

Netspeed Systems

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Asymmetric mesh NoC topologies

System and method for visualization of NoC performance based on simulation output

Asymmetric mesh NoC topologies

Supporting multicast in NoC interconnect

Congestion control and QoS in NoC by regulating the injection traffic

Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements

Supporting multicast in NOC interconnect

Transactional traffic specification for network-on-chip design

System level simulation in network on chip architecture

Heterogeneous channel capacities in an interconnect

Asymmetric mesh NoC topologies

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

System level simulation in Network on Chip architecture

Automatic NoC topology generation

Automatic performance characterization of a network-on-chip (NOC) interconnect

Generation of network-on-chip layout based on user specified topological constraints

Automatic generation of physically aware aggregation/distribution networks

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Heterogeneous channel capacities in an interconnect

Generation of network-on-chip layout based on user specified topological constraints

Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

Hierarchical asymmetric mesh with virtual routers

Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)

Transaction expansion for NoC simulation and NoC design

KUMAR SAILESH

Hierarchical asymmetric mesh with virtual routers

Multiple heterogeneous NoC layers

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

Tagging and synchronization for fairness in NOC interconnects

QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes

NETSPEED SYSTEMS INC

Buffer sizing of a NoC through machine learning

Buffer sizing of a NoC through machine learning

Cost management against requirements for the generation of a NoC

Cost management against requirements for the generation of a NoC

Cost management against requirements for the generation of a NoC

PHILIP JOJI

Automatic construction of deadlock free interconnects

BAYA SYSTEMS INC

Inter-cluster hierarchical routing with multiple paths for load balancing