Inventor

MITRA SUNDARI

US14 patents

⚠️ This page may combine multiple inventors who share the name “MITRA SUNDARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Netspeed Systems

6 patents

US8601423B1Dec 3, 2013

KUMAR SAILESH

5 patents

US9253085B2Feb 2, 2016

Hierarchical asymmetric mesh with virtual routers

KUMAR SAILESH22 citations92

US9130856B2Sep 8, 2015

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

KUMAR SAILESH9 citations83

US9009648B2Apr 14, 2015

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

KUMAR SAILESH17 citations83

US9185026B2Nov 10, 2015

Tagging and synchronization for fairness in NOC interconnects

KUMAR SAILESH5 citations72

US9007920B2Apr 14, 2015

QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes

KUMAR SAILESH3 citations62

INTEL CORP

2 patents

US5481697AJan 2, 1996

An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies

INTEL CORP31 citations91

US5221867AJun 22, 1993

Programmable logic array with internally generated precharge and evaluation timing

INTEL CORP42 citations89

PHILIP JOJI

1 patent

US9244880B2Jan 26, 2016

Automatic construction of deadlock free interconnects

PHILIP JOJI31 citations90

MITRA SUNDARI

Netspeed Systems

Asymmetric mesh NoC topologies

Asymmetric mesh NoC topologies

Heterogeneous channel capacities in an interconnect

Asymmetric mesh NoC topologies

Heterogeneous channel capacities in an interconnect

Hierarchical asymmetric mesh with virtual routers

KUMAR SAILESH

Hierarchical asymmetric mesh with virtual routers

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

Tagging and synchronization for fairness in NOC interconnects

QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes

INTEL CORP

An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies

Programmable logic array with internally generated precharge and evaluation timing

PHILIP JOJI

Automatic construction of deadlock free interconnects