Inventor

YEW TRI-RUNG

TW91 patents

⚠️ This page may combine multiple inventors who share the name “YEW TRI-RUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEW TRI-RUNG

UNITED MICROELECTRONICS CORP

Dual damascene process

Planarization technique for DRAM cell capacitor electrode

Method for manufacturing dielectric layer

Method for fabricating shallow trench isolation structure

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

Method of manufacturing copper interconnect

Process for low k organic dielectric film etch

Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall

Method for forming a DRAM cell electrode

Dual damascence process

Method of fabricating a shallow-trench isolation structure in integrated circuit

Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit

Method for growing hemispherical grain silicon

Method of fabricating dual damascene

Process and structure for embedded DRAM

Method of fabricating a thin and structurally-undefective dielectric structure for a storage capacitor in dynamic random-access memory

Method of patterning dielectric

Dual damascene process

Method of fabricating gate

Method for fabricating a capacitor in a semiconductor device

Fabrication method of a tantalum pentoxide dielectric layer for a DRAM capacitor

Method of fabricating a dynamic random access memory device

Structure of metallization

Method of fabricating a daul damascene structure

Method of forming bonding pad

Method of forming dual damascene structure

Method to fabricate a dual metal-damascene structure in a substrate

Fabricating method of a barrier layer

Method of forming a dual damascene with dummy metal lines

Method for forming charge storage structure

Method of Making High-K Dielectrics for embedded DRAMS

Method of fabricating semiconductor device

Method for manufacturing metal oxide semiconductor transistor having raised source/drain

Method of manufacturing shallow trench isolation

Method of fabricating shallow trench isolation

Method for fabricating gate oxide layer

Method for fabricating semiconductor device

Self-aligned via process for preventing poison via formation

Dual damascene processing method

Method of fabricating a capacitor of a dynamic random access memory

Multi-step spacer formation of semiconductor devices

Method for forming a poly gate structure

Method of fabricating metal-insulator-metal capacitor

Method of forming dual damascene structure

Method of forming dual damascene structure

Method for forming a gate

Via structure and method of manufacture

Method of fabricating an unlanded metal via of multi-level interconnection

Method for increasing capacitance

(unassigned)

Method for unlanded via etching using etch stop