Inventor

HO CHAW SING

SG20 patents

⚠️ This page may combine multiple inventors who share the name “HO CHAW SING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HO CHAW SING

CHARTERED SEMICONDUCTOR MFG

Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration

Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology

MIM and metal resistor formation at CU beol using only one extra mask

Structure and process for a capacitor and other devices

Self-integrated vertical MIM capacitor in the dual damascene process

Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process

Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices

Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions

Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices

Method to fabricate MIM capacitor with a curvillnear surface using damascene process

Method to form uniform silicide features

HEWLETT PACKARD DEVELOPMENT CO

Ink property sensing on a printhead

Apparatuses including a plate having a recess and a corresponding protrusion to define a chamber

Fluid ejection devices comprising memory cells

Electrically-functional optical target

CHARTERED SEMICONDUCTORS MFG L

Method to fabricate MIM capacitor using damascene process

Damascene MIM capacitor with a curvilinear surface structure

HEWLETT PACKARD DEVELOPMENT CO LP

Fluid ejection apparatuses including a substrate with a bulk layer and a epitaxial layer

Memory cell that prevents charge loss

GE NING

Device including active floating gate region area that is smaller than channel area