Inventor

NARDI FEDERICO

US30 patents

⚠️ This page may combine multiple inventors who share the name “NARDI FEDERICO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARDI FEDERICO

INTERMOLECULAR INC

Resistive random access memory cells having shared electrodes with transistor devices

Stacked bi-layer as the low power switchable RRAM

Electron barrier height controlled interfaces of resistive switching layers in resistive random access memory cells

ReRAM cells with diffusion-resistant metal silicon oxide layers

Current-limiting electrodes

Vertical oxide-oxide interface for forming-free, low power and low variability RRAM devices

Current selectors formed using single stack structures

All around electrode for novel 3D RRAM applications

Resistive random access memory cells having variable switching characteristics

Morphology control of ultra-thin MeOx layer

Resistive switching schmitt triggers and comparators

Two stage forming of resistive random access memory cells

Morphology control of ultra-thin MeOx layer

Voltage controlling assemblies including variable resistance devices

Morphology control of ultra-thin MeOx layer

IL-free MIM stack for clean RRAM devices

Resistive switching sample and hold

SANDISK TECHNOLOGIES LLC

Multi-state and confined phase change memory with vertical cross-point structure

Resistive memory device including a lateral air gap around a memory element and method of making thereof

Phase change memory electrode with multiple thermal interfaces

Multi-state phase change memory device with vertical cross-point structure

Methods of forming a phase change memory with vertical cross-point structure

Write-once read-many amorphous chalcogenide-based memory

Threshold switch for memory

In-storage logic for hardware accelerators

Methods of forming a phase change memory with vertical cross-point structure

Vector matrix multiplication with 3D NAND

APPLIED MATERIALS INC

Two-terminal one-time programmable fuses for memory cells

Soft reset for multi-level programming of memory cells in non-von neumann architectures

Soft reset for multi-level programming of memory cells in non-Von Neumann architectures