Inventor

CHEN WEN-HAO

TW105 patents

⚠️ This page may combine multiple inventors who share the name “CHEN WEN-HAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN WEN-HAO

TAIWAN SEMICONDUCTOR MFG CO LTD

Layout boundary method

Integrated circuit and method of forming same and a system

Method of designing semiconductor device

Integrated circuit and method of forming same and a system

Layout for semiconductor device including via pillar structure

Rule checking for multiple patterning technology

Power strap structure for high performance and low current density

Method of generating techfile having reduced corner variation value

Method of cutting conductive patterns

Cell layout design and method

Method and system for replacing a pattern in a layout

Method and system for latch-up prevention

Integrated device and method of forming the same

Method and circuit for via pillar optimization

Electromigration resistant standard cell device

Electromigration resistant standard cell device

Integrated circuit and method of forming same and a system

System for designing semiconductor device

Integrated circuit and method of forming same and a system

Multi-row standard cell design method in hybrid row height system

Via rail solution for high power electromigration

Power strap structure for high performance and low current density

Method of designing semiconductor device and system for implementing the method

Method of decomposing a layout for multiple-patterning lithography

Via rail solution for high power electromigration

Method, system, and storage medium for engineering change order scheme in circuit design

Method of decomposing a layout for multiple-patterning lithography

Power strap structure for high performance and low current density

Method for triple-patterning friendly placement

Characterizing cell using input waveform generation considering different circuit topologies

Cell boundaries for self aligned multiple patterning abutments

Integrated circuit and method of forming the same

Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effect

Cell row arrangement in regions of integrated circuit layout

Integrated device and method of forming the same

Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effect

Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects

Semiconductor process technology assessment

Semiconductor process technology assessment

Multiple driver pin integrated circuit structure

TAIWAN SEMICONDUCTOR MFG

Layout re-decomposition for multiple patterning layouts

Double patterning technology (DPT) layout routing

Generating database for cells routable in pin layer

Systems and methods for designing layouts for semiconductor device fabrication

Method for cell modeling and timing verification of chip designs with voltage drop

CHEN HUANG-YU

Compression method and system for use with multi-patterning

Method and system for replacing a pattern in a layout

LU LEE-CHUNG

Electromigration resistant standard cell device

CHEN WEN-HAO

Fixing full-chip violations using flip-flops

BAVISKAR DINESH

Reducing voltage drops in power networks using unused spaces in integrated circuits