Inventor

Singh Sahil Preet

TW37 patents

Patents

37 patents

US11309000B2Apr 19, 2022

Systems and methods for controlling power management operations in a memory device

TAIWAN SEMICONDUCTOR MFG CO LTD5 citations84

US10734066B2Aug 4, 2020

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations82

US11763863B2Sep 19, 2023

Systems and methods for controlling power management operations in a memory device

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations75

US12165739B2Dec 10, 2024

Systems and methods for controlling power management operations in a memory device

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US11423978B2Aug 23, 2022

Write assist for a memory device and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US11361818B2Jun 14, 2022

Memory device with global and local latches

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73

US10971220B2Apr 6, 2021

Write assist for a memory device and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73

US10535658B2Jan 14, 2020

Memory device with reduced-resistance interconnect

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US10529415B2Jan 7, 2020

Write assist for a memory device and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US10510403B2Dec 17, 2019

Memory read stability enhancement with short segmented bit line architecture

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US10319435B2Jun 11, 2019

Write assist for a memory device and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73

US10153038B2Dec 11, 2018

Memory read stability enhancement with short segmented bit line architecture

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73

US10134737B2Nov 20, 2018

Memory device with reduced-resistance interconnect

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73

US10510401B2Dec 17, 2019

Semiconductor memory device using shared data line for read/write operation

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72

US10790015B2Sep 29, 2020

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations71

US9928899B2Mar 27, 2018

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations71

US12217792B2Feb 4, 2025

Memory circuit and method of operating same

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations64

US12586635B2Mar 24, 2026

Static random access memory with write assist circuit

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US12512150B2Dec 30, 2025

Memory device with global and local latches

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US12272427B2Apr 8, 2025

Semiconductor device including first and second clock generators

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US12074156B2Aug 27, 2024

Memory array circuit and method of manufacturing same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11948627B2Apr 2, 2024

Static random access memory with write assist circuit

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11922998B2Mar 5, 2024

Memory device with global and local latches

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11830544B2Nov 28, 2023

Write assist for a memory device and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11423977B2Aug 23, 2022

Static random access memory with write assist circuit

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11145655B2Oct 12, 2021

Memory device with reduced-resistance interconnect

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US11120868B2Sep 14, 2021

Semiconductor memory device using shared data line for read/write operation

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US10964683B2Mar 30, 2021

Memory array circuit and method of manufacturing the same

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62

US10157666B2Dec 18, 2018

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61

US10854282B2Dec 1, 2020

Memory read stability enhancement with short segmented bit line architecture

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

US10832765B2Nov 10, 2020

Variation tolerant read assist circuit for SRAM

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

US10127951B2Nov 13, 2018

Memory device with reduced-resistance interconnect

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52

US10037796B2Jul 31, 2018

Generating a collapsed VDD using a write-assist column to decrease a write voltage

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52

US10490267B2Nov 26, 2019

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51

Singh Sahil Preet

Patents

Systems and methods for controlling power management operations in a memory device

Static random access memory with write assist circuit

Memory read stability enhancement with short segmented bit line architecture

Circuit with self-adjust pre-charged global data line

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Systems and methods for controlling power management operations in a memory device

Systems and methods for controlling power management operations in a memory device

Write assist for a memory device and methods of forming the same

Memory device with global and local latches

Write assist for a memory device and methods of forming the same

Memory device with reduced-resistance interconnect

Write assist for a memory device and methods of forming the same

Memory read stability enhancement with short segmented bit line architecture

Write assist for a memory device and methods of forming the same

Memory read stability enhancement with short segmented bit line architecture

Memory device with reduced-resistance interconnect

Semiconductor memory device using shared data line for read/write operation

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Memory circuit and method of operating same

Static random access memory with write assist circuit

Memory device with global and local latches

Semiconductor device including first and second clock generators

Memory array circuit and method of manufacturing same

Static random access memory with write assist circuit

Memory device with global and local latches

Write assist for a memory device and methods of forming the same

Static random access memory with write assist circuit

Memory device with reduced-resistance interconnect

Semiconductor memory device using shared data line for read/write operation

Memory array circuit and method of manufacturing the same

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Memory read stability enhancement with short segmented bit line architecture

Variation tolerant read assist circuit for SRAM

Memory device with reduced-resistance interconnect

Generating a collapsed VDD using a write-assist column to decrease a write voltage

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)