Inventor

FANG SHENQING

US97 patents

⚠️ This page may combine multiple inventors who share the name “FANG SHENQING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FANG SHENQING

SPANSION LLC

Method of improving erase voltage distribution for a flash memory array having dummy wordlines

Method and system for tailoring core and periphery cells in a nonvolatile memory

Memory first process flow and device

High voltage gate formation

Dual spacer formation in flash memory

Memory device peripheral interconnects and method of manufacturing

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

Memory gate landing pad made from dummy features

Integrated circuits with non-volatile memory and methods for manufacture

Memory cell with reduced DIBL and Vss resistance

Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability

Self-aligned NAND flash select-gate wordlines for spacer double patterning

Scaled down select gates of NAND flash memory cell strings and method of forming same

Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell

Method for forming a flash memory device with straight word lines

Split charge storage node inner spacer process

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

Method and system for forming straight word lines in a flash memory array

Method and system for forming dual gate structures in a nonvolatile memory using a protective layer

Spacer formation with straight sidewall

Integrated circuit memory system employing silicon rich layers

CYPRESS SEMICONDUCTOR CORP

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

Memory first process flow and device

NAND memory cell string having a stacked select gate structure and process for for forming same

Non-volatile memory array with memory gate line and source line scrambling

Memory first process flow and device

Charge-trap NOR with silicon-rich nitride as a charge trap layer

Split-gate semiconductor device with L-shaped gate

Split gate charge trapping memory cells having different select gate and memory gate heights

Tilted implant for poly resistors

Charge trapping split gate device and method of fabricating same

Memory first process flow and device

NAND memory cell string having a stacked select gate structure and process for forming same

Method of spacer formation with straight sidewall of memory cells

Memory first process flow and device

FANG SHENQING

Memory device interconnects and method of manufacturing

Memory device peripheral interconnects

Memory with extended charge trapping layer

Memory cell system with charge trap

Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory

MONTEREY RES LLC

Varied silicon richness silicon nitride formation

Memory device interconnects and method of manufacture

Memory device interconnects and method of manufacture

ADVANCED MICRO DEVICES INC

Narrow wide spacer

Flash memory cell with drain and source formed by diffusion of a dopant from a silicide

CHEN TUNG-SHENG

Self-aligned NAND flash select-gate wordlines for spacer double patterning

Process margin engineering in charge trapping field effect transistors

ADVANCED MIRCO DEVICES INC

Method and apparatus for eliminating word line bending by source side implantation

KANG INKUK

Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges