Inventor
NAKABAYASHI YOSHIE
JP11 patents
Patents
11 patentsUS11294830B2Apr 5, 2022
Training and operations with a double buffered memory topology
RAMBUS INC8 citations85
US10613995B2Apr 7, 2020
Training and operations with a double buffered memory topology
RAMBUS INC7 citations83
US10169258B2Jan 1, 2019
Memory system design using buffer(s) on a mother board
RAMBUS INC3 citations83
US11768780B2Sep 26, 2023
Training and operations with a double buffered memory topology
RAMBUS INC1 citations72
US12536110B2Jan 27, 2026
Memory system design using buffer(s) on a mother board
RAMBUS INC0 citations62
US12141081B2Nov 12, 2024
Training and operations with a double buffered memory topology
RAMBUS INC0 citations62
US11907139B2Feb 20, 2024
Memory system design using buffer(s) on a mother board
RAMBUS INC0 citations62
US11537540B2Dec 27, 2022
Memory system design using buffer(s) on a mother board
RAMBUS INC0 citations62
US11003601B2May 11, 2021
Memory system design using buffer(s) on a mother board
RAMBUS INC0 citations62
US10255220B2Apr 9, 2019
Dynamic termination scheme for memory communication
RAMBUS INC1 citations60
US10614002B2Apr 7, 2020
Memory system design using buffer(S) on a mother board
RAMBUS INC0 citations51