Inventor

STRACOVSKY HENRY

US28 patents

⚠️ This page may combine multiple inventors who share the name “STRACOVSKY HENRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STRACOVSKY HENRY

INFINEON TECHNOLOGIES AG

Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus

Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution

Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests

Techniques for improving memory access in a virtual memory system

Methods and apparatus for prioritization of access to external devices

Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory

Universal resource access controller

Methods and apparatus for prioritization of access to external devices

Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses

Universal memory controller

Computer memory conflict avoidance using page registers

Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M

RAMBUS INC

Training and operations with a double buffered memory topology

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Memory system design using buffer(s) on a mother board

Memory system design using buffer(s) on a mother board

Memory system design using buffer(S) on a mother board

INTEL CORP

Error detection and correction apparatus and method

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

INFINEON AG

Methods and apparatus for prediction of the time between two consecutive memory accesses

INFINEION TECHNOLOGIES AG

Using of bank tag registers to avoid a background operation collision in memory systems

STRACOVSKY HENRY

Reliability support in memory systems without error correcting code support

QUALCOMM INC

Explicit lockstep for functional safety