Inventor

KIRSCH HOWARD C

US98 patents

⚠️ This page may combine multiple inventors who share the name “KIRSCH HOWARD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIRSCH HOWARD C

MOTOROLA INC

Method for forming isolation regions in a semiconductor device

Semiconductor device having a static-random-access memory cell

Process for forming an electrically programmable read-only memory cell

Method for forming a nonvolatile memory device

Vertical field-effect transistor and a semiconductor memory cell having the transistor

Interconnection structure for conductive layers

Methods of forming a vertical field-effect transistor and a semiconductor memory cell

Method for forming a via structure and semiconductor device having the same

Method for planarizing a layer of material

Method for forming a nested surface capacitor

Method for forming an interconnection structure for conductive layers

Three-dimensionally integrated nonvolatile SRAM cell and process

Electrically programmable read-only memory cell

Semiconductor device and method of formation

Ferroelectric memory cell and method of sensing and writing the polarization state thereof

Process for the formation of elevated source and drain structures in a semiconductor device

Plural transistor silicon on insulator structure with shared electrodes

Method of forming recessed oxide isolation

Method for forming a semiconductor device

MICRON TECHNOLOGY INC

Trench buried bit line memory devices

Delay-locked loop circuit and method using a ring oscillator and counter-based delay

Open digit line array architecture for a memory array

Trench buried bit line memory devices and methods thereof

Delay-locked loop circuit and method using a ring oscillator and counter-based delay

Multiple-depth STI trenches in integrated circuit fabrication

Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage

Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals

Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals

Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

Memory structure having volatile and non-volatile memory portions

Open digit line array architecture for a memory array

Trench buried bit line memory devices and methods thereof

Multiple-depth STI trenches in integrated circuit fabrication

Level shifter for low voltage operation

VANGUARD INT SEMICONDUCT CORP

Design for high density memory with relaxed metal pitch

Word line resistance reduction method and design for high density memory with relaxed metal pitch

Method for forming a capacitor with a multiple pillar structure

Schmitt trigger input stage

Multiple-bit, current mode data bus

Integrated circuit output driver incorporating power distribution noise suppression circuitry

AT & T BELL LAB

Fast column access memory

Integrated circuit having a variably boosted node

AMERICAN TELEPHONE & TELEGRAPH

IGFET gating circuit having reduced electric field degradation

Zero standby current TTL to CMOS input buffer

BELL TELEPHONE LABOR INC

Current control circuit for light emitting diode

THOMSON COMPONENTS MOSTEK CORP

Sense amplifier for a dynamic RAM

JUENGLING WERNER

Double gated 4F2 dram CHC cell and methods of fabricating the same

KIM TAE H

Line driver circuits, methods, and apparatuses

KIM TAE

Memory device word line drivers and methods