Inventor

MIRKARIMI LAURA WILLS

US70 patents

⚠️ This page may combine multiple inventors who share the name “MIRKARIMI LAURA WILLS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIRKARIMI LAURA WILLS

ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Processed stacked dies

Metal pads over TSV

Techniques for processing devices

TSV as pad

Bonded structures with integrated passive component

Low temperature bonded structures

Direct bonded stack structures for increased reliability and improved yield in microelectronics

Techniques for joining dissimilar materials in microelectronics

Techniques for processing devices

TSV as pad

Low temperature bonded structures

Dimension compensation control for directly bonded structures

Structures for bonding elements including conductive interface features

Direct bonded stack structures for increased reliability and improved yield in microelectronics

Low temperature bonded structures

Low temperature bonded structures

Processed stacked dies

Microelectronic assembly from processed substrate

Mitigating surface damage of probe pads in preparation for direct bonding of a substrate

Dimension compensation control for directly bonded structures

Bonded structure with active interposer

INVENSAS BONDING TECH INC

Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics

Processed stacked dies

Low temperature bonded structures

Large metal pads over TSV

Microelectronic assembly from processed substrate

Mitigating surface damage of probe pads in preparation for direct bonding of a substrate

Techniques for processing devices

Bonded structures

Techniques for processing devices

Direct bonded stack structures for increased reliability and improved yield in microelectronics

Microelectronic assembly from processed substrate

Low temperature bonded structures

Selective recess

INVENSAS CORP

Interconnect structures and methods for forming same

Integrated circuit assemblies with reinforcement frames, and methods of manufacture

Integrated circuit assemblies with reinforcement frames, and methods of manufacture

Multi-layer substrates suitable for interconnection between circuit modules

Wafer-level packaging using wire bond wires in place of a redistribution layer

Fan-out wafer-level packaging using metal foil lamination

Wafer level packages with mechanically decoupled fan-in and fan-out areas

AGILENT TECHNOLOGIES INC

Post-etch cleaning treatment

Photonic crystal sensors

Oriented rhombohedral composition of PbZr1-xTixO3 thin films for low voltage operation ferroelectric RAM

Barrier layers ferroelectric memory devices

TESSERA INC

Reconstituted wafer level stacking

Off-chip vias in stacked chips

HABA BELGACEM

Off-chip VIAS in stacked chips

AVAGO TECH FIBER IP SG PTE LTD

Method for etching smooth sidewalls in III-V based compounds for electro-optical devices

ADEIA SEMICONDUCTOR TECH LLC

Methods for bonding semiconductor elements