Inventor

THAREJA GAURAV

US64 patents

⚠️ This page may combine multiple inventors who share the name “THAREJA GAURAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THAREJA GAURAV

KEPLER COMPUTING INC

Doped polar layers and semiconductor device incorporating same

Low power ferroelectric based majority logic gate adder

B-site doped perovskite layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Low power ferroelectric based majority logic gate carry propagate and serial adder

Majority logic gate based sequential circuit

Majority logic gate fabrication

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Manganese-doped perovskite layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

B-site doped perovskite layers and semiconductor device incorporating same

Low power ferroelectric based majority logic gate multiplier

Integration method of ferroelectric memory array

Linear input and non-linear output threshold logic gate

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Pillar capacitor and method of fabricating such

Low power ferroelectric based majority logic gate adder

Linear input and non-linear output majority logic gate

Linear input and non-linear output majority logic gate with and/or function

Pillar capacitor and method of fabricating such

Integration of ferroelectric memory devices having stacked electrodes with transistors

Ferroelectric capacitor integrated with logic

Integration of ferroelectric memory devices with transistors

Integration of a ferroelectric memory device with a transistor

Ferroelectric capacitor integrated with logic

Ferroelectric capacitor and method of patterning such

Multiplier with non-linear polar material

Majority gate based low power ferroelectric based adder with reset mechanism

APPLIED MATERIALS INC

Methods and apparatus for metal silicide deposition

Semiconductor device, method of making a semiconductor device, and processing system

Airgap formation processes

Processing system and method of forming a contact

Method of fabricating a semiconductor device having reduced contact resistance

GLASS GLENN A

Self-aligned 3-D epitaxial structures for MOS device fabrication

Conversion of thin transistor elements from silicon to silicon germanium