Inventor
KUMAR DHULIPALLA PHANEENDRA
IN7 patents
Patents
7 patentsUS11442108B1Sep 13, 2022
Isolation logic test circuit and associated test method
ST MICROELECTRONICS INT NV4 citations69
US11513544B1Nov 29, 2022
Reset and safe state logic generation in dual power flow devices
ST MICROELECTRONICS INT NV4 citations67
US11860993B2Jan 2, 2024
Dynamic randomization of password challenge
ST MICROELECTRONICS INT NV0 citations57
US11227046B2Jan 18, 2022
Dynamic randomization of password challenge
ST MICROELECTRONICS INT NV0 citations57
US11281795B2Mar 22, 2022
Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips
ST MICROELECTRONICS INT NV0 citations47
US11983025B2May 14, 2024
Reset and safe state logic generation in dual power flow devices
ST MICROELECTRONICS INT NV0 citations46
US12580790B2Mar 17, 2026
Controller area network extra-long (CAN-XL) low latency hardware and software partitioned architecture for message handler
ST MICROELECTRONICS INT NV0 citations39