Inventor

ASANOVIC KRSTE

US25 patents

⚠️ This page may combine multiple inventors who share the name “ASANOVIC KRSTE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASANOVIC KRSTE

SIFIVE INC

Load-store pipeline selection for vectors

Macro-op fusion

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

Macro-op fusion

Macro-op fusion for pipelined architectures

Checker cores for fault tolerant processing

Checker cores for fault tolerant processing

Address range encoding in system on a chip with securely partitioned memory space

Error management in system on a chip with securely partitioned memory space

Technologies for prediction-based register renaming

Efficient processing of masked memory accesses

Fusion with destructive instructions

Memory protection for vector operations

Memory protection for gather-scatter operations

Secure predictors for speculative execution

Technologies for interconnect address remapper with event recognition and register management

Secure control flow prediction

INT COMPUTER SCIENCE INST

Vector processing system with multi-operation, run-time configurable pipelines

MASSACHUSETTS INST TECHNOLOGY

System and technique for fine-grained computer memory protection

SILICON GRAPHICS INTERNAT

System and method for performing memory operations in a computing system

SILICON GRAPHICS INC

System and method for performing memory operations in a computing system

MILLER STEVEN C

System and method for performing memory operations in a computing system