Inventor

CHANG CHI

US114 patents

⚠️ This page may combine multiple inventors who share the name “CHANG CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG CHI

ADVANCED MICRO DEVICES INC

Automatic program disturb with intelligent soft programming for flash cells

Flash EEPROM array with high endurance

Flash EEPROM array with negative gate voltage erase operation

Trench side wall charge trapping dielectric flash memory device

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure

Process for fabricating an integrated circuit with a self-aligned contact

Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS

One transistor flash EPROM cell

Method of erasing non-volatile memory cells

Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory

Memory device having A P+ gate and thin bottom oxide and method of erasing same

Flash memory array with dual function control lines and asymmetrical source and drain junctions

Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space

Salicided gate for virtual ground arrays

Salicided gate for virtual ground arrays

Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer

Semiconductor device with self-aligned contacts using a liner oxide layer

Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide

Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device

Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method

Memory cell programming with controlled current injection

Channel hot-carrier page write

Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch

Non-volatile memory structure including protection and structure for maintaining threshold stability

Nonvolatile memory cell with a nitridated oxide layer

Method of channel hot electron programming for short channel NOR flash arrays

Non-volatile memory device with encapsulated tungsten gate and method of making same

Method of making tungsten gate MOS transistor and memory cell by encapsulating

Symmetrical program and erase scheme to improve erase time degradation in NAND devices

Method of forming dual field isolation structures

Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory

Non-volatile storage device refresh time detector

Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices

Method and device for programming cells in a memory array in a narrow distribution

Flash memory cell programming method and system

Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory

Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation

Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process

VIA TECH INC

System for latching an output signal generated by comparing complimentary strobe signals and a data signal in response to a comparison of the complimentary strobe signals

Duty-cycle adjustable buffer and method and method for operating same

Clock-signal adjusting method and device

Method and circuit for generating memory clock signal

Bus receiver and method of deskewing bus signals

Circuit calibrating output driving strength of DRAM and method thereof

Data-sampling strobe signal generator and input buffer using the same

SPANSION LLC

Dual charge storage node memory device and methods for fabricating such device

Flash memory with buried bit lines

(unassigned)

Using floating gate devices as select gate devices for NAND flash memory and its bias scheme