Inventor

RAMSBEY MARK T

US118 patents

⚠️ This page may combine multiple inventors who share the name “RAMSBEY MARK T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMSBEY MARK T

ADVANCED MICRO DEVICES INC

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Use of high-k dielectric materials in modified ONO structure for semiconductor devices

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Bitline hard mask spacer flow for memory cell scaling

Semiconductor memory with deuterated materials

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Planar structure for non-volatile memory devices

Method of simultaneous formation of bitline isolation and periphery oxide

Source drain implant during ONO formation for improved isolation of SONOS devices

Disposable hard mask for memory bitline scaling

Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer

Method of fabricating double densed core gates in sonos flash memory

Simultaneous formation of charge storage and bitline to wordline isolation

Simultaneous formation of charge storage and bitline to wordline isolation

Laser thermal annealing methods for flash memory devices

Implant damage removal by laser thermal annealing

Laser thermal annealing method for high dielectric constant gate oxide films

Memory device and method of making

Flash memory with controlled wordline width

Salicided gate for virtual ground arrays

Memory device and method of making

Salicided gate for virtual ground arrays

Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer

Semiconductor device with self-aligned contacts using a liner oxide layer

Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method

Memory device having silicided bitlines and method of forming the same

Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Charge-trapping memory arrays resistant to damage from contact hole information

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

High density dual bit flash memory cell with non planar structure

Memory manufacturing process using bitline rapid thermal anneal

Memory wordline hard mask

Method of making memory wordline hard mask extension

Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory

Method for removing anti-reflective coating layer using plasma etch process after contact CMP

Method of forming dual field isolation structures

Hard mask spacer for sublithographic bitline

Method of making a memory cell with polished insulator layer

Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation

Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics

Backside wafer polishing for improved photolithography

Buried silicide local interconnect with sidewall spacers and method for making the same

Flash NVROM devices with UV charge immunity

FASL LLC

Memory device having high work function gate and method of erasing same

Recessed channel with separated ONO memory device

Method of manufacturing a semiconductor memory with deuterated materials

Dummy wordline for erase and bitline leakage

SPANSION LLC

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process