Inventor

WHETSEL LEE D

US842 patents

⚠️ This page may combine multiple inventors who share the name “WHETSEL LEE D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WHETSEL LEE D

TEXAS INSTRUMENTS INC

Selectable JTAG or trace access with data store and output

IC with state machine controlled linking module

Generator/compactor scan circuit low power adapter with counter

Hierarchical access of test access ports in embedded core integrated circuits

Probeless testing of pad buffers on wafer

Selectively accessing test access ports in a multiple test access port environment

Addressable shadow port and protocol for serial bus networks

IC interposer with TAP controller and output boundary scan cell

Scan, test, and control circuits coupled to IC surfaces contacts

Integrated circuits carrying intellectual property cores and test ports

Controller for scan distributor and controller architecture

TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports

System scan path architecture

IC with comparator receiving expected and mask data from pads

IC having comparator inputs connected to core circuitry and output pad

Comparator circuitry connected to input and output of tristate buffer

Address and TMS gating circuitry for TAP control circuit

TAP domain selection circuit with AUXI/O1 or TDI lead

DDR input interface to IC test controller circuitry

TAM controller for plural test access mechanisms

JTAG circuit transferring data between devices on TCK terminals

Controller receiving combined TMS/TDI and suppyling separate TMS and TDI

Connection of auxiliary circuitry to tap and instruction register controls

JTAG circuit transferring data between devices on TMS terminals

Removable and replaceable TAP domain selection circuitry

Tap and test controller with separate enable inputs

Means scanning scan path parts sequentially and capturing response simultaneously

IC tap/scan test port access with tap lock circuitry

Link instruction register providing test control signals to core wrappers

IC with two state machines connected to serial scan path

Scan circuit low power adapter with counter

Position independent testing of circuits

Process of testing a semiconductor wafer of IC dies

Process of controlling plural test access ports

Parallel scan distributors and collectors and process of testing integrated circuits

Die testing using top surface test pads

IC with addressable test port

Circuitry and method of transferring parallel and serial data

Accelerating scan test by re-using response data as stimulus data

Position independent testing of circuits

Semiconductor wafer with connecting leads between the dies

Parallel scan distributors and collectors and process of testing integrated circuits

IP core design supporting user-added scan register option

Boundary scan input output serializer (BIOS) circuit

Process of testing integrated circuit dies on a wafer

Method and apparatus for streamlined testing of electrical circuits

Fault tolerant selection of die on wafer

Semiconductor wafer with interconnect between dies for testing and a process of testing

WHETSEL LEE D

AT speed TAP with dual port router and command circuit

Serial compressed data I/O in a parallel test compression architecture