Inventor
EICHELBERGER EDWARD BAXTER
8 patents
Patents
8 patentsUS4063080ADec 13, 1977
Method of propagation delay testing a level sensitive array logic system
IBM48 citations93
US4051352ASep 27, 1977
Level sensitive embedded array logic system
IBM41 citations93
US4074851AFeb 21, 1978
Method of level sensitive testing a functional logic system with embedded array
IBM35 citations89
US4071902AJan 31, 1978
Reduced overhead for clock testing in a level system scan design (LSSD) system
IBM23 citations80
US4006492AFeb 1, 1977
High density semiconductor chip organization
IBM23 citations80
US4063078ADec 13, 1977
Clock generation network for level sensitive logic system
IBM18 citations66
US3986057AOct 12, 1976
High performance latch circuit
IBM4 citations61
US5852367ADec 22, 1998
Speed enhanced level shifting circuit utilizing diode capacitance
IBM6 citations56