Inventor
PERLEGOS GEORGE
US16 patents
⚠️ This page may combine multiple inventors who share the name “PERLEGOS GEORGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS4266283AMay 5, 1981
Electrically alterable read-mostly memory
INTEL CORP55 citations96
US4223394ASep 16, 1980
Sensing amplifier for floating gate memory devices
INTEL CORP93 citations96
US4203158AMay 13, 1980
Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
INTEL CORP317 citations95
US4519849AMay 28, 1985
Method of making EPROM cell with reduced programming voltage
INTEL CORP30 citations91
US4094012AJun 6, 1978
Electrically programmable MOS read-only memory with isolated decoders
INTEL CORP41 citations91
US3938108AFeb 10, 1976
Erasable programmable read-only memory
INTEL CORP36 citations91
US4114255ASep 19, 1978
Floating gate storage device and method of fabrication
INTEL CORP38 citations90
US4264828AApr 28, 1981
MOS Static decoding circuit
INTEL CORP21 citations82
US4103189AJul 25, 1978
Mos buffer circuit
INTEL CORP22 citations81
US4412310AOct 25, 1983
EPROM Cell with reduced programming voltage and method of fabrication
INTEL CORP14 citations72
SEEQ TECHNOLOGY INC
6 patentsUS4546454AOct 8, 1985
Non-volatile memory cell fuse element
SEEQ TECHNOLOGY INC59 citations96
US4558344ADec 10, 1985
Electrically-programmable and electrically-erasable MOS memory device
SEEQ TECHNOLOGY INC37 citations92
US4538245AAug 27, 1985
Enabling circuit for redundant word lines in a semiconductor memory array
SEEQ TECHNOLOGY INC38 citations92
US4535259AAug 13, 1985
Sense amplifier for use with a semiconductor memory array
SEEQ TECHNOLOGY INC28 citations92
US4768169AAug 30, 1988
Fault-tolerant memory array
SEEQ TECHNOLOGY INC15 citations73
US4489401ADec 18, 1984
Electrical partitioning scheme for improving yields during the manufacture of semiconductor memory arrays
SEEQ TECHNOLOGY INC12 citations73