Inventor

PANCHOLY ASHISH

US21 patents

⚠️ This page may combine multiple inventors who share the name “PANCHOLY ASHISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANCHOLY ASHISH

CYPRESS SEMICONDUCTOR CORP

Synchronous random access memory having a read/write address bus and process for writing to and reading from the same

Random access memory having a read/write address bus and process for writing to and reading from the same

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Random access memory having independent read port and write port and process for writing to and reading from the same

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Scan path circuitry including a programmable delay circuit

Scan path circuitry for programming a variable clock pulse width

Test mode features for synchronous pipelined memories

Scan path circuitry including an output register having a flow through mode

Scan path circuitry including a programmable delay circuit

Method and apparatus for self-resetting logic circuitry

Method and apparatus to prevent latch-up in CMOS devices

Multi-level programmable voltage control and output buffer with selectable operating voltage

Multi-level programmable voltage control and output buffer with selectable operating voltage

Method and apparatus for reducing skew among input signals within an integrated circuit

Random access memory having independent read port and write port and process for writing to and reading from the same

Eye-safe laser navigation sensor

SILICON MAGNETIC SYSTEMS

Magnetic memory cell and method for assigning tunable writing currents

MRAM data line configuration and method of operation

Memory circuit with selective address path

Localized MRAM data line and method of operation