Inventor

DOSAKA KATSUMI

JP123 patents

⚠️ This page may combine multiple inventors who share the name “DOSAKA KATSUMI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOSAKA KATSUMI

MITSUBISHI ELECTRIC CORP

Multi-bank dRAM suitable for integration with processor on common semiconductor chip

Semiconductor memory device with improved buffer for generating internal write designating signal and operating method thereof

Dynamic semiconductor memory device superior in refresh characteristics

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Microcomputer with processor bus having smaller width than memory bus

Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester

Multi-bank DRAM suitable for integration with processor on common semiconductor chip

Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM

Multi-bank DRAM suitable for integration with processor on common semiconductor chip

Clock synchronous semiconductor memory device for determining an operation mode

Synchronous type semiconductor memory device having internal operation timings determined by count values of an internal counter

Synchronous semiconductor memory device suitable for graphic data processing

Clock synchronous semiconductor memory device

Semiconductor memory device

Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM

Semiconductor memory device

Semiconductor memory device

Clock synchronous semiconductor memory device

Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor

Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein

Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor

Self-refreshing of dynamic random access memory device and operating method therefor

Dynamic random access memory device and operating method therefor

Semiconductor memory device having on-chip error check and correction functions

Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor memory device

Synchronous semiconductor memory including register for storing data input and output mode information

Synchronous semiconductor memory device with multi-bank configuration

Semiconductor memory device with an internal voltage generating circuit

Semiconductor memory device having a circuit for fast operation

Synchronous semiconductor memory device with multi-bank configuration

Semiconductor integrated circuit device with adjustable high voltage detection circuit

Synchronous semiconductor memory device with multi-bank configuration

Semiconductor memory capable of transferring data at a high speed between an SRAM and a DRAM array

Dynamic random access memory device capable of performing test mode operation and method of operating such memory device

Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof

Circuit having charge compensation and an operation method of the same

Voltage boosting circuit and operating method thereof

Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof

Semiconductor memory device with improved immunity to supply voltage fluctuations

Semiconductor memory device with an improved multi-bit test mode

Circuit for generating a boosted signal for a word line

RENESAS TECH CORP

Semiconductor device and semiconductor signal processing apparatus

Semiconductor device and semiconductor signal processing apparatus

WATANABE NAOYA

Content addressable memory