Inventor

LOVETT SIMON J

US64 patents

⚠️ This page may combine multiple inventors who share the name “LOVETT SIMON J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOVETT SIMON J

MICRON TECHNOLOGY INC

Temperature sensing device in an integrated circuit

Detection circuit for mixed asynchronous and synchronous memory operation

Detection circuit for mixed asynchronous and synchronous memory operation

Detection circuit for mixed asynchronous and synchronous memory operation

Asynchronous interface circuit and method for a pseudo-static memory device

Zero power chip standby mode

Apparatuses and methods for countering memory attacks

Memory device latch circuitry

Array plate short repair

Block erase for volatile memory

Apparatuses and methods for implementing masked write commands

Detection circuit for mixed asynchronous and synchronous memory operation

Temperature sensing device in an integrated circuit

Method and apparatus for synchronizing data from memory arrays

Method and apparatus for synchronizing data from memory arrays

Asynchronous interface circuit and method for a pseudo-static memory device

Zero power chip standby mode

Method and apparatus for enabling a digital memory tester to read the frequency of a free running oscillator

Power-efficient generation of voltage

Setting local power domain timeout via temperature sensor systems and methods

Systems, methods, and apparatuses for temperature and process corner sensitive control of power gated domains

Power-efficient generation of voltage

Plate defect mitigation techniques

Memory device latch circuitry

Block erase for volatile memory

Method and apparatus for synchronizing data from memory arrays

Method of operating a dynamic random access memory cell

Apparatus and method for improving dynamic refresh in a memory device

Method of rewriting a logic state of a memory cell

Apparatus and method for improving dynamic refresh in a memory device

Method of operating a dynamic random access memory cell

Redundancy and swapping scheme for memory repair

Zero power chip standby mode

CYPRESS SEMICONDUCTOR CORP

Synchronous random access memory having a read/write address bus and process for writing to and reading from the same

Nonvolatile cell

Buffer with stable trip point

Threshold voltage mismatch compensated sense amplifier for SRAM memory arrays

Symmetrical nand gates

Random access memory having a read/write address bus and process for writing to and reading from the same

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Random access memory having independent read port and write port and process for writing to and reading from the same

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Symmetrical NOR gates

Buffer with stable trip point

Random access memory having independent read port and write port and process for writing to and reading from the same

LOVETT SIMON J

Method for measuring a temperature in an electronic device having a battery and a memory device

Method and apparatus for synchronizing data from memory arrays

Maintenance of amplified signals using high-voltage-threshold transistors

Detection circuit for mixed asynchronous and synchronous memory operation

ROUND ROCK RES LLC

Method for measuring a temperature in an electronic device having a battery