Inventor

CHAPPELL BARBARA A

US25 patents

⚠️ This page may combine multiple inventors who share the name “CHAPPELL BARBARA A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAPPELL BARBARA A

IBM

Pipelined memory chip structure having improved cycle time

SRAM cell with capacitor

Virtual multi-port RAM

Virtual multi-port RAM employing multiple accesses during single machine cycle

Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories

Multi-stage pass transistor shifter/rotator

High-performance, high-density CMOS decoder/driver circuit

Fast comparator circuit

Fast cycle time clocked amplifier

High speed decoding circuit with improved AND gate

High speed CMOS logic device for providing ECL compatible logic levels

Source-follower emitter-coupled-logic receiver circuit

Multiplying interface circuit for level shifting between FET and TTL levels

Heterojunction semiconductor

High performance FET driver circuit

Heterojunction semiconductor

Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability

Transporsable memory architecture

Complementary input circuit with nonlinear front end and partially coupled latch

INTEL CORP

VDD modulated SRAM for highly scaled, high performance cache

High speed ratioed CMOS logic structures for a pulsed input environment

Multi version library cell handling and integrated circuit structures fabricated therefrom

Multi version library cell handling and integrated circuit structures fabricated therefrom

BOHR MARK T

Through gate fin isolation

CHAPPELL BARBARA A

High spatial resolution energy discriminator