Inventor
WITT DAVID B
US106 patents
Patents
50 patentsUS5651125AJul 22, 1997
High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
ADVANCED MICRO DEVICES INC398 citations99
US6256728B1Jul 3, 2001
Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction
ADVANCED MICRO DEVICES INC113 citations98
US6141747AOct 31, 2000
System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
ADVANCED MICRO DEVICES INC135 citations98
US6112293AAug 29, 2000
Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
ADVANCED MICRO DEVICES INC91 citations98
US6094716AJul 25, 2000
Register renaming in which moves are accomplished by swapping rename tags
ADVANCED MICRO DEVICES INC96 citations98
US5860104AJan 12, 1999
Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates
ADVANCED MICRO DEVICES INC262 citations98
US5796973AAug 18, 1998
Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions
ADVANCED MICRO DEVICES INC97 citations98
US5689672ANov 18, 1997
Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
ADVANCED MICRO DEVICES INC99 citations98
US5623627AApr 22, 1997
Computer memory architecture including a replacement cache
ADVANCED MICRO DEVICES INC99 citations98
US6189068B1Feb 13, 2001
Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
ADVANCED MICRO DEVICES INC88 citations97
US6505292B1Jan 7, 2003
Processor including efficient fetch mechanism for L0 and L1 caches
ADVANCED MICRO DEVICES INC59 citations96
US6308259B1Oct 23, 2001
Instruction queue evaluating dependency vector in portions during different clock phases
ADVANCED MICRO DEVICES INC60 citations96
US6279101B1Aug 21, 2001
Instruction decoder/dispatch
ADVANCED MICRO DEVICES INC56 citations96
US6266752B1Jul 24, 2001
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
ADVANCED MICRO DEVICES INC53 citations96
US6212622B1Apr 3, 2001
Mechanism for load block on store address generation
ADVANCED MICRO DEVICES INC59 citations96
US6212623B1Apr 3, 2001
Universal dependency vector/queue entry
ADVANCED MICRO DEVICES INC50 citations96
US6088789AJul 11, 2000
Prefetch instruction specifying destination functional unit and read/write access mode
ADVANCED MICRO DEVICES INC49 citations96
US5987561ANov 16, 1999
Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
ADVANCED MICRO DEVICES INC60 citations96
US5944815AAug 31, 1999
Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access
ADVANCED MICRO DEVICES INC85 citations96
US5867682AFeb 2, 1999
High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations
ADVANCED MICRO DEVICES INC58 citations96
US5867683AFeb 2, 1999
Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
ADVANCED MICRO DEVICES INC47 citations96
US5835753ANov 10, 1998
Microprocessor with dynamically extendable pipeline stages and a classifying circuit
ADVANCED MICRO DEVICES INC72 citations96
US5828869AOct 27, 1998
Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism
ADVANCED MICRO DEVICES INC73 citations96
US5805912ASep 8, 1998
Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor
ADVANCED MICRO DEVICES INC54 citations96
US5768555AJun 16, 1998
Reorder buffer employing last in buffer and last in line bits
ADVANCED MICRO DEVICES INC53 citations96
US5751981AMay 12, 1998
High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format
ADVANCED MICRO DEVICES INC53 citations96
US5664136ASep 2, 1997
High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations
ADVANCED MICRO DEVICES INC66 citations96
US5655098AAug 5, 1997
High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format
ADVANCED MICRO DEVICES INC49 citations96
US5623619AApr 22, 1997
Linearly addressable microprocessor cache
ADVANCED MICRO DEVICES INC42 citations96
US5357626AOct 18, 1994
Processing system for providing an in circuit emulator with processor internal state
ADVANCED MICRO DEVICES INC99 citations96
US5059818AOct 22, 1991
Self-regulating clock generator
ADVANCED MICRO DEVICES INC63 citations96
US6553482B1Apr 22, 2003
Universal dependency vector/queue entry
ADVANCED MICRO DEVICES INC40 citations93
US6457117B1Sep 24, 2002
Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address
ADVANCED MICRO DEVICES INC19 citations93
US6393546B1May 21, 2002
Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values
ADVANCED MICRO DEVICES INC21 citations93
US6332191B1Dec 18, 2001
System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor
ADVANCED MICRO DEVICES INC41 citations93
US6321326B1Nov 20, 2001
Prefetch instruction specifying destination functional unit and read/write access mode
ADVANCED MICRO DEVICES INC25 citations93
US6266763B1Jul 24, 2001
Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values
ADVANCED MICRO DEVICES INC18 citations93
US6256721B1Jul 3, 2001
Register renaming in which moves are accomplished by swapping tags
ADVANCED MICRO DEVICES INC24 citations93
US6240503B1May 29, 2001
Cumulative lookahead to eliminate chained dependencies
ADVANCED MICRO DEVICES INC18 citations93
US6237082B1May 22, 2001
Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
ADVANCED MICRO DEVICES INC20 citations93
US6202139B1Mar 13, 2001
Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing
ADVANCED MICRO DEVICES INC44 citations93
US6199154B1Mar 6, 2001
Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
ADVANCED MICRO DEVICES INC25 citations93
US6167506ADec 26, 2000
Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
ADVANCED MICRO DEVICES INC16 citations93
US6161167ADec 12, 2000
Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group
ADVANCED MICRO DEVICES INC50 citations93
US6157986ADec 5, 2000
Fast linear tag validation unit for use in microprocessor
ADVANCED MICRO DEVICES INC50 citations93
US6134649AOct 17, 2000
Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
ADVANCED MICRO DEVICES INC23 citations93
US6122656ASep 19, 2000
Processor configured to map logical register numbers to physical register numbers using virtual register numbers
ADVANCED MICRO DEVICES INC36 citations93
US6122727ASep 19, 2000
Symmetrical instructions queue for high clock frequency scheduling
ADVANCED MICRO DEVICES INC39 citations93
US6119223ASep 12, 2000
Map unit having rapid misprediction recovery
ADVANCED MICRO DEVICES INC43 citations93
US6112296AAug 29, 2000
Floating point stack manipulation using a register map and speculative top of stack values
ADVANCED MICRO DEVICES INC28 citations93
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