Inventor
SMITH HOWARD H
US25 patents
⚠️ This page may combine multiple inventors who share the name “SMITH HOWARD H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS7093206B2Aug 15, 2006
Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
IBM30 citations92
US6546529B1Apr 8, 2003
Method for performing coupling analysis
IBM25 citations92
US6418401B1Jul 9, 2002
Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
IBM24 citations92
US6323050B1Nov 27, 2001
Method for evaluating decoupling capacitor placement for VLSI chips
IBM26 citations91
US7971171B2Jun 28, 2011
Method and system for electromigration analysis on signal wiring
IBM13 citations84
US6460169B1Oct 1, 2002
Routing program method for positioning unit pins in a hierarchically designed VLSI chip
IBM18 citations84
US6374394B1Apr 16, 2002
Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip
IBM16 citations84
US7319946B2Jan 15, 2008
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
IBM6 citations73
US6415428B1Jul 2, 2002
Minimal length method for positioning unit pins in a hierarchically designed VLSI chip
IBM13 citations73
US6618844B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM8 citations72
US6618843B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM9 citations72
US6333680B1Dec 25, 2001
Method and system for characterizing coupling capacitance between integrated circuit interconnects
IBM10 citations70
US9582622B1Feb 28, 2017
Evaluating on-chip voltage regulation
IBM4 citations68
US7844435B2Nov 30, 2010
Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
IBM4 citations62
US6963204B2Nov 8, 2005
Method to include delta-I noise on chip using lossy transmission line representation for the power mesh
IBM5 citations62
US7346877B2Mar 18, 2008
Decoupling capacitance analysis method
IBM3 citations61
US7269806B2Sep 11, 2007
Decoupling capacitance analysis method
IBM4 citations61
US7086026B2Aug 1, 2006
Decoupling capacitance analysis method
IBM4 citations61
US9607118B1Mar 28, 2017
Evaluating on-chip voltage regulation
IBM1 citations47
US10467372B2Nov 5, 2019
Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designs
IBM0 citations36