Inventor
CAMPORESE PETER J
US13 patents
Patents
13 patentsUS6311313B1Oct 30, 2001
X-Y grid tree clock distribution network with tunable tree and grid networks
IBM196 citations98
US6205571B1Mar 20, 2001
X-Y grid tree tuning method
IBM104 citations97
US6546529B1Apr 8, 2003
Method for performing coupling analysis
IBM25 citations92
US6487706B1Nov 26, 2002
Contract methodology for concurrent hierarchical design
IBM67 citations92
US6629298B1Sep 30, 2003
Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design
IBM24 citations91
US6323050B1Nov 27, 2001
Method for evaluating decoupling capacitor placement for VLSI chips
IBM26 citations91
US5455931AOct 3, 1995
Programmable clock tuning system and method
IBM54 citations91
US6460169B1Oct 1, 2002
Routing program method for positioning unit pins in a hierarchically designed VLSI chip
IBM18 citations84
US6374394B1Apr 16, 2002
Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip
IBM16 citations84
US6415428B1Jul 2, 2002
Minimal length method for positioning unit pins in a hierarchically designed VLSI chip
IBM13 citations73
US6618843B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM9 citations72
US6618844B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM8 citations72
US6341365B1Jan 22, 2002
Method for automating the placement of a repeater device in an optimal location, considering pre-defined blockages, in high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designs
IBM3 citations54