Inventor

TAO HUN-JAN

TW142 patents

⚠️ This page may combine multiple inventors who share the name “TAO HUN-JAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAO HUN-JAN

TAIWAN SEMICONDUCTOR MFG

Method of trimming technology

Top corner rounding for shallow trench isolation

Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher

Backside contacts for MOS devices

Partial resist free approach in contact etch to improve W-filling

Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material

Chemistry for etching organic low-k materials

Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask

Hard mask method for forming chlorine containing plasma etched layer

Method of fabricating a MOSFET device with metal containing gate structures

Plasma etch method for forming patterned oxygen containing plasma etchable layer

Post gate etch cleaning process for self-aligned gate mosfets

Method of dual damascene etching

Method of patterning narrow gate electrode

Reactive ion etch method for forming vias through nitrogenated silicon oxide layers

Method to form a semiconductor device having gate dielectric layers of varying thicknesses

Photoresist intensive patterning and processing

Method using wet etching to trim a critical dimension

Bi-layer photoresist dry development and reactive ion etch method

Method of making borderless contact having a sion buffer layer

Process flow to optimize profile of ultra small size photo resist free contact

Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity

Method of forming dual damascene structure with improved contact/via edge integrity

Process for forming an integrated contact or via

Post photodevelopment isotropic radiation treatment method for forming patterned photoresist layer with attenuated linewidth

Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width

Method for patterning a polysilicon gate in deep submicron technology

HCL in overetch with hard mask to improve metal line etching profile

Dry etching endpoint procedure to protect against photolithographic misalignments

Optical emisson spectroscopy (OES) method for monitoring and controlling plasma etch process when forming patterned layers

Etch rate monitoring by optical emission spectroscopy

Method and apparatus for backside polymer reduction in dry-etch process

Resolving pattern-loading issues of SiGe stressor

Semiconductor devices with dual-metal gate structures and fabrication methods thereof

Gate structure and method of forming the gate dielectric with mini-spacer

Approach to improve line end shortening

Dual hard mask layer patterning method

Silicon shallow trench etching with round top corner by photoresist-free process

Methods of adhesion promoter between low-K layer and underlying insulating layer

Method for improving faceting effect in dual damascene process

Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer

Method of forming a shallow trench isolation using oxide slope etching

Multi-metal-oxide high-K gate dielectrics

Method of making a metal-insulator-metal capacitor in the CMOS process

Integrated approach for controlling top dielectric loss during spacer etching

Process for removing organic materials during formation of a metal interconnect

Dynamic feed forward temperature control to achieve CD etching uniformity

Recessed polysilicon gate structure for a strained silicon MOSFET device

TAIWAN SEMICONDUCTOR MANFACTUR

Method for cleaning silicon wafers with deep trenches

CHANG HONG-DYI

Method for protecting a gate structure during contact formation