Inventor

DEBBAGE MARK

GB22 patents

⚠️ This page may combine multiple inventors who share the name “DEBBAGE MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEBBAGE MARK

INTEL CORP

Reliable transport architecture

Scalable protocol-agnostic reliable transport

System, method and apparatus for improving the performance of collective operations in high performance computing

Optimized credit return mechanism for packet sends

Sending packets using optimized PIO write sequences without SFENCEs

Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same

System for storage of received messages

Direct memory writes by network interface of a graphics processing unit

Technologies for managing a latency-efficient pipeline through a network interface controller

System, apparatus, and method for streaming input/output data

Sending packets using optimized PIO write sequences without SFENCES

Optimized credit return mechanism for packet sends

Optimized credit return mechanism for packet sends

Sending packets using optimized PIO write sequences without sfences

Sending packets using optimized PIO write sequences without sfences

Packet format adjustment technologies

Sending packets using optimized PIO write sequences without sfences and out of order credit returns

HITACHI LTD

Microprocessor having improved memory management unit and cache memory

Microprocessor having improved memory management unit and cache memory

Microprocessor having improved memory management unit and cache memory

SUN MICROSYSTEMS INC

Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes

HEINZ MICHAEL

System, method and apparatus for improving the performance of collective operations in high performance computing