Inventor

GABRIEL CALVIN T

US68 patents

⚠️ This page may combine multiple inventors who share the name “GABRIEL CALVIN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GABRIEL CALVIN T

ADVANCED MICRO DEVICES INC

Selective photoresist hardening to facilitate lateral trimming

Post-treatment of low-k dielectric for prevention of photoresist poisoning

Pre-treatment of low-k dielectric for prevention of photoresist poisoning

Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant

Method for reducing critical dimension attainable via the use of an organic conforming layer

Line edge roughness reduction by plasma treatment before etch

Slot via filled dual damascene interconnect structure without middle etch stop layer

Plasma etch process for nonhomogenous film

Via filled dual damascene structure with middle stop layer and method for making the same

Semiconductor device with variable composition low-k inter-layer dielectric and method of making

Dielectric layer with treated top surface forming an etch stop layer and method of making the same

Silicon carbide barc in dual damascene processing

Method of making a via filled dual damascene structure without middle stop layer

Attenuated phase shift mask for use in EUV lithography and a method of making such a mask

EUV mask or reticle having reduced reflections

Quantifying and predicting the impact of line edge roughness on device reliability and performance

Silicon-containing resist to pattern organic low k-dielectrics

Using scatterometry to verify contact hole opening during tapered bilayer etch

System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process

Process for improving the etch stability of ultra-thin photoresist

Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning

Carrier gas modification for preservation of mask layer during plasma etching

Ultra thin etch stop layer for damascene process

Method of making a dual damascene structure without middle stop layer

Methods for designing grating structures for use in situ scatterometry to detect photoresist defects

Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set

Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure

Method to improve ignition in plasma etching or plasma deposition steps

N-containing plasma etch process with reduced resist poisoning

Use of hydrogen doping for protection of low-k dielectric layers

VLSI TECHNOLOGY INC

Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication

Optimized structures for dummy fill mask design

Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Method and apparatus for detecting imminent end-point when etching dielectric layers in a plasma etch system

Method for making anti-fuse structures

Anti-fuse structures and methods for making same

System and method for plasma etching endpoint detection

Method for leak detection in etching chambers

Semiconductor processing method for preventing corrosion of metal film connections

Method and apparatus for patterning a metal layer

Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges

Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Method for making shallow trench isolation structure having rounded corners

Method and apparatus for wafer level prediction of thin oxide reliability using differentially sized gate-like antennae

Method and apparatus for wafer level prediction of thin oxide reliability

Method for making cusp-free anti-fuse structures

Endpoint detection system and method for plasma etching

Gas phase planarization process for semiconductor wafers

PHILIPS ELECTRONICS NA

Intelligent gate-level fill methods for reducing global pattern density effects

Method for reducing faceting on a photoresist layer during an etch process