Inventor

ARGHAVANI REZA

US56 patents

⚠️ This page may combine multiple inventors who share the name “ARGHAVANI REZA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARGHAVANI REZA

INTEL CORP

Method for making a semiconductor device having a high-k gate dielectric

N2 O nitrided-oxide trench sidewalls and method of making isolation structure

Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

Method for making a semiconductor device having a high-k gate dielectric

Integrated circuit with multiple gate dielectric structures

Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode

Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors

Plasma nitridation for reduced leakage gate dielectric layers

Method for making a semiconductor device having a high-k gate dielectric

Method of forming gate oxide having dual thickness by oxidation process

Pre-etch implantation damage for the removal of thin film layers

N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress

Integrated circuit with multiple gate dielectric structures

Plasma nitridation for reduced leakage gate dielectric layers

Method for making a semiconductor device having a high-k gate dielectric

Semiconductor on insulator apparatus

Semiconductor on insulator apparatus and method

Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress

Thin oxides of silicon

Thin dielectric layers and non-thermal formation thereof

Field effect transistor

Method of processing a substrate

Method and apparatus for dry/catalytic-wet steam oxidation of silicon

Semiconductor on insulator apparatus

APPLIED MATERIALS INC

Method for producing gate stack sidewall spacers

Post treatment of low k dielectric films

Method for forming a low thermal budget spacer

Low-thermal-budget gapfill process

Memory cell having stressed layers

Substrate having silicon germanium material and stressed silicon nitride layer

Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill

Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill

Method of forming non-volatile memory having charge trap layer with compositional gradient

Oxide etch with NH4-NF3 chemistry

Substrate having silicon germanium material and stressed silicon nitride layer

Method of inducing stresses in the channel region of a transistor

LAM RES CORP

Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors

Integrated etch/clean for dielectric etch applications

CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications

Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors

Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS

Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors

Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask

UNIV TOHOKU

Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer

Semiconductor devices including cobalt alloys and fabrication methods thereof

INTEL COROPORATION

Advanced trench sidewall oxide for shallow trench technology

MIE FUJITSU SEMICONDUCTOR LTD

Transistor with threshold voltage set notch and method of fabrication thereof

ARGHAVANI REZA

Transistor with threshold voltage set notch and method of fabrication thereof

BALSEANU MIHAELA

Method of forming a non-volatile memory having a silicon nitride charge trap layer