Inventor

PRASAD CHANDRIKA

US34 patents

Patents

34 patents

US6599778B2Jul 29, 2003

Process for making fine pitch connections between devices and structure made by the process

IBM65 citations96

US5534466AJul 9, 1996

Method of making area direct transfer multilayer thin film structure

IBM76 citations96

US6281452B1Aug 28, 2001

Multi-level thin-film electronic packaging structure and related method

IBM53 citations95

US5757079AMay 26, 1998

Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure

IBM90 citations95

US6329609B1Dec 11, 2001

Method and structure to prevent distortion and expansion of organic spacer layer for thin film transfer-join technology

IBM64 citations94

US7564118B2Jul 21, 2009

Chip and wafer integration process using vertical connections

IBM23 citations93

US7388277B2Jun 17, 2008

Chip and wafer integration process using vertical connections

IBM20 citations93

US7049697B2May 23, 2006

Process for making fine pitch connections between devices and structure made by the process

IBM22 citations93

US6737297B2May 18, 2004

Process for making fine pitch connections between devices and structure made by the process

IBM32 citations93

US6640021B2Oct 28, 2003

Fabrication of a hybrid integrated circuit device including an optoelectronic chip

IBM47 citations93

US4518112AMay 21, 1985

Process for controlled braze joining of electronic packaging elements

IBM37 citations93

US6678949B2Jan 20, 2004

Process for forming a multi-level thin-film electronic packaging structure

IBM21 citations92

US6444919B1Sep 3, 2002

Thin film wiring scheme utilizing inter-chip site surface wiring

IBM29 citations92

US6090633AJul 18, 2000

Multiple-plane pair thin-film structure and process of manufacture

IBM46 citations92

US5747095AMay 5, 1998

Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages

IBM28 citations92

US6099935AAug 8, 2000

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

IBM24 citations91

US6998327B2Feb 14, 2006

Thin film transfer join process and multilevel thin film module

IBM27 citations88

US6669833B2Dec 30, 2003

Process and apparatus for electroplating microscopic features uniformly across a large substrate

IBM20 citations88

US6724203B1Apr 20, 2004

Full wafer test configuration using memory metals

IBM13 citations84

US6632314B1Oct 14, 2003

Method of making a lamination and surface planarization for multilayer thin film interconnect

IBM14 citations82

US5464682ANov 7, 1995

Minimal capture pads applied to ceramic vias in ceramic substrates

IBM13 citations73

US6149048ANov 21, 2000

Apparatus and method for use in manufacturing semiconductor devices

IBM7 citations72

US6323045B1Nov 27, 2001

Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process

IBM10 citations69

US4634041AJan 6, 1987

Process for bonding current carrying elements to a substrate in an electronic system, and structures thereof

IBM10 citations69

US4407860AOct 4, 1983

Process for producing an improved quality electrolessly deposited nickel layer

IBM11 citations65

US6448169B1Sep 10, 2002

Apparatus and method for use in manufacturing semiconductor devices

IBM5 citations61

US5916451AJun 29, 1999

Minimal capture pads applied to ceramic vias in ceramic substrates

IBM4 citations61

US4714982ADec 22, 1987

Substrate for a semiconductor package having improved I/O pin bonding

IBM1 citations47

PRASAD CHANDRIKA

Patents

Chip and wafer integration process using vertical connections

Interconnect structure having improved metallization

Method of fabricating integrated electronic chip with an interconnect device

Thin film attachment to laminate using a dendritic interconnection

Chip and wafer integration process using vertical connections

Three-dimensional integrated CMOS-MEMS device and process for making the same

Process for making fine pitch connections between devices and structure made by the process

Method of making area direct transfer multilayer thin film structure

Multi-level thin-film electronic packaging structure and related method

Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure

Method and structure to prevent distortion and expansion of organic spacer layer for thin film transfer-join technology

Chip and wafer integration process using vertical connections

Chip and wafer integration process using vertical connections

Process for making fine pitch connections between devices and structure made by the process

Process for making fine pitch connections between devices and structure made by the process

Fabrication of a hybrid integrated circuit device including an optoelectronic chip

Process for controlled braze joining of electronic packaging elements

Process for forming a multi-level thin-film electronic packaging structure

Thin film wiring scheme utilizing inter-chip site surface wiring

Multiple-plane pair thin-film structure and process of manufacture

Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

Thin film transfer join process and multilevel thin film module

Process and apparatus for electroplating microscopic features uniformly across a large substrate

Full wafer test configuration using memory metals

Method of making a lamination and surface planarization for multilayer thin film interconnect

Minimal capture pads applied to ceramic vias in ceramic substrates

Apparatus and method for use in manufacturing semiconductor devices

Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process

Process for bonding current carrying elements to a substrate in an electronic system, and structures thereof

Process for producing an improved quality electrolessly deposited nickel layer

Apparatus and method for use in manufacturing semiconductor devices

Minimal capture pads applied to ceramic vias in ceramic substrates

Substrate for a semiconductor package having improved I/O pin bonding