Inventor

DIETRICH STEFAN

DE94 patents

⚠️ This page may combine multiple inventors who share the name “DIETRICH STEFAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIETRICH STEFAN

INFINEON TECHNOLOGIES AG

Circuit configuration with a memory array

Latency time circuit for an S-DRAM

Method and circuit arrangement for controlling write access to a semiconductor memory

Latency time switch for an S-DRAM

Integrated memory with a block writing function and global amplifiers requiring less space

Circuit for data bit inversion

Read latency control circuit

Register for the parallel-serial conversion of data

Integrated circuit and method for testing it

DDR memory and storage method

Parallel-serial converter

Integrated memory having a row access controller for activating and deactivating row lines

Memory component with short access time

Synchronous integrated memory

Integrated memory

Method and device for data transfer

Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

Method and circuit configuration for read-write mode control of a synchronous memory

Memory including an output pointer circuit

Method and circuit arrangement for resetting an integrated circuit

SIEMENS AG

Integrated memory having column decoder for addressing corresponding bit line

Device for the laser processing of flat workpieces

Apparatus for the automated processing of workpieces

Integrated memory

Integrated memory

Method of producing an aluminum film

TEXAS INSTRUMENTS INC

Method and system for buck converter current re-use for minimum switching frequency pulse-skip operation

Seamless DCM-PFM transition for single pulse operation in DC-DC converters

Power supply system with pulse mode operation

Timer for creating a stable on time

Switched-mode DC/DC converter having a bootstrapped high-side driver

Power transistor gate-charge harvester for internal supply generation

MICRON TECHNOLOGY INC

Error detection code hold pattern synchronization

Bit and signal level mapping

Error detection code hold pattern synchronization

Data inversion techniques

Postamble for multi-level signal modulation

Bit and signal level mapping

QIMONDA AG

Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device

Semiconductor memory circuit, circuit arrangement and method for reading out data

Memory device and method of operating such

Apparatus and method of operating an integrated circuit

Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency

SEW EURODRIVE GMBH & CO

Gearbox with a shaft

Bearing system and gear unit

DIETRICH STEFAN

Method to enhance neural tissue operation

CERBOMED GMBH

Device for applying a transcutaneous stimulus or for transcutaneous measuring of a parameter

3M INNOVATIVE PROPERTIES CO

Slidable fastener bearing assembly

BARTON PETER

Cooling system and geared motor

LODESTAR LICENSING GROUP LLC

Bit and signal level mapping