Inventor

SCHROEGMEIER PETER

DE42 patents

⚠️ This page may combine multiple inventors who share the name “SCHROEGMEIER PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHROEGMEIER PETER

INFINEON TECHNOLOGIES AG

Circuit configuration with a memory array

Latency time circuit for an S-DRAM

Method and circuit arrangement for controlling write access to a semiconductor memory

Latency time switch for an S-DRAM

Integrated memory with a block writing function and global amplifiers requiring less space

Read latency control circuit

Method and device for initializing an asynchronous latch chain

Register for the parallel-serial conversion of data

Integrated circuit and method for testing it

DDR memory and storage method

Parallel-serial converter

Integrated memory having a row access controller for activating and deactivating row lines

Memory component with short access time

Synchronous integrated memory

Integrated memory

Method and device for data transfer

Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

Method and circuit configuration for read-write mode control of a synchronous memory

Method and circuit arrangement for resetting an integrated circuit

Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock

Device for driving a memory cell of a memory module by means of a charge store

Integrated memory, and a method of operating an integrated memory

Integrated memory with two burst operation types

Integrated memory having redundant units of memory cells, and test method for the redundant units

Circuit configuration for programming a delay in a signal path

Integrated memory

Control circuit for an S-DRAM

Integrated circuit and method for operating the integrated circuit

Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory

Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated

Voltage pump with switch-on control

Integrated circuit having a command decoder

Integrated memory having memory cells disposed at crossover points of word lines and bit lines

SIEMENS AG

Integrated memory having column decoder for addressing corresponding bit line

Integrated memory

Integrated memory

Semiconductor memory having differential bit lines

QIMONDA AG

Systems and methods for writing to a memory

Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device

Integrated circuit with Resistivity changing memory cells and methods of operating the same

Apparatus and method of operating an integrated circuit

(unassigned)

Method of reducing voice signal interference