Inventor

PRADEEP YELEHANKA RAMACHANDRAM

SG52 patents

Patents

50 patents

US6300177B1Oct 9, 2001

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

CHARTERED SEMICONDUCTOR MFG175 citations99

US6461900B1Oct 8, 2002

Method to form a self-aligned CMOS inverter using vertical device integration

CHARTERED SEMICONDUCTOR MFG141 citations98

US6313008B1Nov 6, 2001

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

CHARTERED SEMICONDUCTOR MFG90 citations98

US6277683B1Aug 21, 2001

Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

CHARTERED SEMICONDUCTOR MFG98 citations97

US6406945B1Jun 18, 2002

Self-aligned floating gate for memory application using shallow trench isolation

CHARTERED SEMICONDUCTOR MFG64 citations94

US5866448AFeb 2, 1999

Procedure for forming a lightly-doped-drain structure using polymer layer

CHARTERED SEMICONDUCTOR MFG58 citations94

US6716693B1Apr 6, 2004

Method of forming a surface coating layer within an opening within a body by atomic layer deposition

CHARTERED SEMICONDUCTOR MFG49 citations93

US6709934B2Mar 23, 2004

Method for forming variable-K gate dielectric

CHARTERED SEMICONDUCTOR MFG26 citations93

US6511884B1Jan 28, 2003

Method to form and/or isolate vertical transistors

CHARTERED SEMICONDUCTOR MFG48 citations93

US6468877B1Oct 22, 2002

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

CHARTERED SEMICONDUCTOR MFG53 citations93

US6455377B1Sep 24, 2002

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

CHARTERED SEMICONDUCTOR MFG21 citations93

US6436770B1Aug 20, 2002

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

CHARTERED SEMICONDUCTOR MFG45 citations93

US6417056B1Jul 9, 2002

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

CHARTERED SEMICONDUCTOR MFG51 citations93

US6306715B1Oct 23, 2001

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

CHARTERED SEMICONDUCTOR MFG46 citations93

US6156598ADec 5, 2000

Method for forming a lightly doped source and drain structure using an L-shaped spacer

CHARTERED SEMICONDUCTOR MFG51 citations93

US6468853B1Oct 22, 2002

Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner

CHARTERED SEMICONDUCTOR MFG83 citations92

US6387765B2May 14, 2002

Method for forming an extended metal gate using a damascene process

CHARTERED SEMICONDUCTOR MFG19 citations92

US6316304B1Nov 13, 2001

Method of forming spacers of multiple widths

CHARTERED SEMICONDUCTOR MFG60 citations92

US6211008B1Apr 3, 2001

Method for forming high-density high-capacity capacitor

CHARTERED SEMICONDUCTOR MFG27 citations92

US6346468B1Feb 12, 2002

Method for forming an L-shaped spacer using a disposable polysilicon spacer

CHARTERED SEMICONDUCTOR MFG39 citations91

US6294480B1Sep 25, 2001

Method for forming an L-shaped spacer with a disposable organic top coating

CHARTERED SEMICONDUCTOR MFG24 citations91

US6277700B1Aug 21, 2001

High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

CHARTERED SEMICONDUCTOR MFG52 citations91

US6248006B1Jun 19, 2001

CMP uniformity

CHARTERED SEMICONDUCTOR MFG27 citations91

US6228770B1May 8, 2001

Method to form self-sealing air gaps between metal interconnects

CHARTERED SEMICONDUCTOR MFG35 citations91

US5858847AJan 12, 1999

Method for a lightly doped drain structure

CHARTERED SEMICONDUCTOR MFG44 citations91

US6355581B1Mar 12, 2002

Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability

CHARTERED SEMICONDUCTOR MFG52 citations90

US6566208B2May 20, 2003

Method to form elevated source/drain using poly spacer

CHARTERED SEMICONDUCTOR MFG22 citations89

US6451704B1Sep 17, 2002

Method for forming PLDD structure with minimized lateral dopant diffusion

CHARTERED SEMICONDUCTOR MFG59 citations88

US6300251B1Oct 9, 2001

Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon

CHARTERED SEMICONDUCTOR MFG29 citations88

US6461887B1Oct 8, 2002

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

CHARTERED SEMICONDUCTOR MFG18 citations84

US6380088B1Apr 30, 2002

Method to form a recessed source drain on a trench side wall with a replacement gate technique

CHARTERED SEMICONDUCTOR MFG19 citations84

US6541327B1Apr 1, 2003

Method to form self-aligned source/drain CMOS device on insulated staircase oxide

CHARTERED SEMICONDUCTOR MFG8 citations74

US6436774B1Aug 20, 2002

Method for forming variable-K gate dielectric

CHARTERED SEMICONDUCTOR MFG8 citations74

US6303449B1Oct 16, 2001

Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP

CHARTERED SEMICONDUCTOR MFG12 citations74

US6852605B2Feb 8, 2005

Method of forming an inductor with continuous metal deposition

CHARTERED SEMICONDUCTOR MFG10 citations73

US6306714B1Oct 23, 2001

Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide

CHARTERED SEMICONDUCTOR MFG8 citations72

US6660642B2Dec 9, 2003

Toxic residual gas removal by non-reactive ion sputtering

CHARTERED SEMICONDUCTOR MFG7 citations69

US6200887B1Mar 13, 2001

Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits

CHARTERED SEMICONDUCTOR MFG10 citations68

US6312999B1Nov 6, 2001

Method for forming PLDD structure with minimized lateral dopant diffusion

CHARTERED SEMICONDUCTOR MFG13 citations65

US6440800B1Aug 27, 2002

Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers

CHARTERED SEMICONDUCTOR MFG5 citations63

US6417054B1Jul 9, 2002

Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide

CHARTERED SEMICONDUCTOR MFG5 citations63

US6821904B2Nov 23, 2004

Method of blocking nitrogen from thick gate oxide during dual gate CMP

CHARTERED SEMICONDUCTOR MFG3 citations62

US6281093B1Aug 28, 2001

Method to reduce trench cone formation in the fabrication of shallow trench isolations

CHARTERED SEMICONDUCTOR MFG6 citations62

Showing the top 50 of 52 patents by PatentIndex Score.

PRADEEP YELEHANKA RAMACHANDRAM

Patents

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Self aligned T-top gate process integration

Method for forming dual gate oxide

Method for forming an extended metal gate using a damascene process

Method for forming a T-gate for better salicidation

Method to form an L-shaped silicon nitride sidewall spacer

Self-aligned floating gate for memory application using shallow trench isolation

Procedure for forming a lightly-doped-drain structure using polymer layer

Method of forming a surface coating layer within an opening within a body by atomic layer deposition

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Method for forming a lightly doped source and drain structure using an L-shaped spacer

Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner

Method for forming an extended metal gate using a damascene process

Method of forming spacers of multiple widths

Method for forming high-density high-capacity capacitor

Method for forming an L-shaped spacer using a disposable polysilicon spacer

Method for forming an L-shaped spacer with a disposable organic top coating

High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

CMP uniformity

Method to form self-sealing air gaps between metal interconnects

Method for a lightly doped drain structure

Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability

Method to form elevated source/drain using poly spacer

Method for forming PLDD structure with minimized lateral dopant diffusion

Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

Method to form a recessed source drain on a trench side wall with a replacement gate technique

Method to form self-aligned source/drain CMOS device on insulated staircase oxide

Method for forming variable-K gate dielectric

Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP

Method of forming an inductor with continuous metal deposition

Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide

Toxic residual gas removal by non-reactive ion sputtering

Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits

Method for forming PLDD structure with minimized lateral dopant diffusion

Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers

Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide

Method of blocking nitrogen from thick gate oxide during dual gate CMP

Method to reduce trench cone formation in the fabrication of shallow trench isolations