Inventor

QUEK ELGIN

SG105 patents

⚠️ This page may combine multiple inventors who share the name “QUEK ELGIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QUEK ELGIN

CHARTERED SEMICONDUCTOR MFG

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Modulation of stress in stress film through ion implantation and its application in stress memorization technique

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Material architecture for the fabrication of low temperature transistor

Method to form a self-aligned CMOS inverter using vertical device integration

Method of fabricating variable length vertical transistors

Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Method to form elevated source/drain using poly spacer

Method of forming a pocket implant region after formation of composite insulator spacers

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Method to fabricate a single gate with dual work-functions

Forming dual gate oxide thickness on vertical transistors by ion implantation

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate

Method to form a recessed source drain on a trench side wall with a replacement gate technique

Thyristor-based SRAM

Selective STI stress relaxation through ion implantation

Shallow amorphizing implant for gettering of deep secondary end of range defects

Method of fabricating CMOS device with dual gate electrode

Method of integrating L-shaped spacers in a high performance CMOS process via use of an oxide-nitride-doped oxide spacer

Method to form self-aligned source/drain CMOS device on insulated staircase oxide

Method for forming variable-K gate dielectric

TOH ENG HUAT

Self-aligned contact for replacement metal gate and silicide last processes

Nano-electro-mechanical system (NEMS) structures with actuatable semiconductor fin on bulk substrates

FinFET with stressors

LDMOS with two gate stacks having different work functions for improved breakdown voltage

Finfet

LDMOS with improved breakdown voltage

Compact RRAM device and methods of making same

Three dimensional RRAM device, and methods of making same

GLOBALFOUNDRIES SG PTE LTD

Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current

Transistor devices having an anti-fuse configuration and methods of forming the same

LDMOS with improved breakdown voltage

Semiconductor device with reduced contact resistance and method of manufacturing thereof

Fin selector with gated RRAM

FinFET

Corner transistor suppression

TAN SHYUE SENG

Diffusion barrier and method of formation thereof

Memory cell with decoupled channels

Double gated flash memory