Inventor

SUNDARESAN RAVI

US29 patents

⚠️ This page may combine multiple inventors who share the name “SUNDARESAN RAVI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNDARESAN RAVI

CHARTERED SEMICONDUCTOR MFG

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method of forming contact to polysilicon gate for MOS devices

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Method to form a self-aligned CMOS inverter using vertical device integration

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance

Method of patterning gate electrode with ultra-thin gate dielectric

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

Method to form a recessed source drain on a trench side wall with a replacement gate technique

Method to form self-aligned source/drain CMOS device on insulated staircase oxide

Method for forming variable-K gate dielectric

Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP

Process having high tolerance to buried contact mask misalignment by using a PSG spacer

Process having high tolerance to buried contact mask misalignment by using a PSG spacer

Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide

Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel

Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers

Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide

ST MICROELECTRONICS INC

CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor

Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor