Inventor

PAN YANG

SG168 patents

⚠️ This page may combine multiple inventors who share the name “PAN YANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN YANG

CHARTERED SEMICONDUCTOR MFG

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method of making self-aligned halo process for reducing junction capacitance

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

New chemical mechanical planarization (CMP) end point detection apparatus

Method to form a self-aligned CMOS inverter using vertical device integration

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Method for forming a polycide gate electrode

Method for minimizing the hot carrier effect in N-MOSFET devices

Method of making a conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control

Way to fabricate the self-aligned T-shape gate to reduce gate resistivity

Method and apparatus for determination of the end point in chemical mechanical polishing

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Method for forming a high areal capacitance planar capacitor

Substrate with gate electrode polysilicon/gate oxide stack covered with fluorinated silicon oxide layer and fluorinated corners of gate oxide layer

Back-end capacitor with high unit capacitance

Use of spacers as floating gates in EEPROM with doubled storage efficiency

Method of making low profile shallow trench double polysilicon capacitor

Polysilicon gate reoxidation in a gas mixture of oxygen and nitrogen trifluoride gas by rapid thermal processing to improve hot carrier immunity

Method of forming integrated CMP stopper and analog capacitor

Method for fabricating a planar field oxide region

Method and structure to make planar analog capacitor on the top of a STI structure

Method to form elevated source/drain using poly spacer

Transistors with low overlap capacitance

LAM RES CORP

Photoresist development with halide chemistries

Tin oxide films in semiconductor device manufacturing

Tin oxide films in semiconductor device manufacturing

Etching substrates using ale and selective deposition

Tin oxide films in semiconductor device manufacturing

Integrated dry processes for patterning radiation photoresist patterning

Tin oxide mandrels in patterning

INVENSENSE INC

Transmit beamforming of a two-dimensional array of ultrasonic transducers

Transmit operation of an ultrasonic sensor

PAN YANG

Advertisement delivering system based on digital television system and mobile communication device

Delivering personalized media items to users of interactive television and personal mobile devices by using scrolling tickers

MILLENNIUM BIOTHERAPEUTICS INC

Nucleic acid molecules encoding Tango-77-polypeptides

Neurotactin and uses therefor

HUAWEI DEVICE CO LTD

Modem

(unassigned)

Method for reducing silicided poly gate resistance for very small transistors

CHARTERED SEMICONDUCTOR MFG CO

Semiconductor manufacturing system

CHARTERED SEMICONDUCTOR

Conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control

MILLENIUM BIOTHERAPEUTICS INC

Neurotactin and uses therefor

CHARTERED SEMICONDUCTION MANUF

Method for forming a high areal capacitance planar capacitor