Inventor

JOHNSON BRIAN

US241 patents

⚠️ This page may combine multiple inventors who share the name “JOHNSON BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOHNSON BRIAN

MICRON TECHNOLOGY INC

Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device

Calibration technique for memory devices

Method and system for delay control in synchronization circuits

Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same

Method and apparatus for setting and compensating read latency in a high speed DRAM

Predictive timing calibration for memory devices

Timing calibration pattern for SLDRAM

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

System latency levelization for read data

Memory device and method having data path with multiple prefetch I/O configurations

Method and apparatus for crossing clock domain boundaries

Method and apparatus for calibrating driver impedance

Memory system and method for strobing data, command and address signals

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Memory system and method for strobing data, command and address signals

Memory system and method for strobing data, command and address signals

Method and structures for reduced parasitic capacitance in integrated circuit metallizations

Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Memory system and method for strobing data, command and address signals

Apparatus and method for clock domain crossing with integrated decode

Multiphase clock generators

Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM

Method and structures for reduced parasitic capacitance in integrated circuit metallizations

Multiphase clock generators

Memory device and method having data path with multiple prefetch I/O configurations

Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM

Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system

Apparatus for setting write latency

Memory device and method having data path with multiple prefetch I/O configurations

Memory device and method having data path with multiple prefetch I/O configurations

Method and apparatus providing improved data path calibration for memory devices

Method and apparatus for setting write latency

Double-edged clocked storage device and method

ALTERA CORP

PLD architecture for flexible placement of IP function blocks

Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter

Programmable logic device logic modules with shift register capabilities

DIVICOM INC

MPEG transport stream remultiplexer

MPEG transport stream remultiplexer

Transport stream decoder/demultiplexer for hierarchically organized audio-video streams

SONY ERICSSON MOBILE COMM AB

Display screen with a graphical user interface

Display screen with a graphical user interface

(unassigned)

Bicycle carrier for vehicle

NORTEL NETWORKS LTD

Use of location awareness to establish and suspend communications sessions in a healthcare environment

MIRCON TECHNOLOGY INC

Synchronized write data on a high speed memory bus

HARMONIC INC

Recording and playback of audio-video transport streams

Vero Biotech LLC

Conversion of nitrogen dioxide (NO2) to nitric oxide (NO)

NAT INSTR CORP

Specifying timing and triggering functionality in a graphical program using graphical program nodes

MOTOROLA INC

Channel acquistion and handoff method and apparatus for a TDMA communication system