Inventor
FLACHS BRIAN
US27 patents
⚠️ This page may combine multiple inventors who share the name “FLACHS BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7533238B2May 12, 2009
Method for limiting the size of a local storage of a processor
IBM17 citations91
US7447602B1Nov 4, 2008
System and method for sorting processors based on thermal design point
IBM27 citations91
US10169013B2Jan 1, 2019
Arranging binary code based on call graph partitioning
IBM5 citations84
US7486096B2Feb 3, 2009
Method and apparatus for testing to determine minimum operating voltages in electronic devices
IBM9 citations84
US7203608B1Apr 10, 2007
Impedane measurement of chip, package, and board power supply system using pseudo impulse response
IBM10 citations83
US7610531B2Oct 27, 2009
Modifying a test pattern to control power supply noise
IBM7 citations73
US9916144B2Mar 13, 2018
Arranging binary code based on call graph partitioning
IBM1 citations63
US8359435B2Jan 22, 2013
Optimization of software instruction cache by line re-ordering
IBM4 citations60
US7689865B2Mar 30, 2010
Middlesoft commander
IBM4 citations57
US10324694B2Jun 18, 2019
Arranging binary code based on call graph partitioning
IBM0 citations52
US9606922B2Mar 28, 2017
Selection of post-request action based on combined response and input from the request source
IBM0 citations52
US9547597B2Jan 17, 2017
Selection of post-request action based on combined response and input from the request source
IBM0 citations52
US7730279B2Jun 1, 2010
System for limiting the size of a local storage of a processor
IBM0 citations50
CHEN TONG
8 patentsUS8522225B2Aug 27, 2013
Rewriting branch instructions using branch stubs
CHEN TONG18 citations92
US8782381B2Jul 15, 2014
Dynamically rewriting branch instructions in response to cache line eviction
CHEN TONG7 citations84
US8713548B2Apr 29, 2014
Rewriting branch instructions using branch stubs
CHEN TONG6 citations84
US8631225B2Jan 14, 2014
Dynamically rewriting branch instructions to directly target an instruction cache location
CHEN TONG7 citations84
US8516230B2Aug 20, 2013
SPE software instruction cache
CHEN TONG10 citations83
US9459851B2Oct 4, 2016
Arranging binary code based on call graph partitioning
CHEN TONG3 citations73
US8627051B2Jan 7, 2014
Dynamically rewriting branch instructions to directly target an instruction cache location
CHEN TONG5 citations73
US9600253B2Mar 21, 2017
Arranging binary code based on call graph partitioning
CHEN TONG1 citations62
FLACHS BRIAN
4 patentsUS8520740B2Aug 27, 2013
Arithmetic decoding acceleration
FLACHS BRIAN56 citations95
US8683185B2Mar 25, 2014
Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
FLACHS BRIAN2 citations61
US8862827B2Oct 14, 2014
Efficient multi-level software cache using SIMD vector permute functionality
FLACHS BRIAN0 citations40
US8677101B2Mar 18, 2014
Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file
FLACHS BRIAN0 citations39