Inventor

JOHNS CHARLES R

US68 patents

⚠️ This page may combine multiple inventors who share the name “JOHNS CHARLES R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOHNS CHARLES R

IBM

Method, system, and computer program product for displaying images of conference call participants

Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range

Method for limiting the size of a local storage of a processor

Livelock resolution method

System and method for communicating command parameters between a processor and a memory flow controller

Two dimensional frame buffer memory interface system and method of operation thereof

Preloading translation buffers

Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing store with reserve and load when reservation lost instructions

Load when reservation lost instruction for performing cacheline polling

Method and apparatus for testing to determine minimum operating voltages in electronic devices

Communicating instructions and data between a processor and external devices

Method for communicating instructions and data between a processor and external devices

Priority control in resource allocation for low request rate, latency-sensitive units

Method for communicating with a processor event facility

Digital thermal sensor test implementation without using main core voltage supply

Security for address translation services

Identifying location of data granules in global virtual address space

Caching data from remote memories

Distributed directory of named data elements in coordination namespace

Peripheral component interconnect express (PCIE) pseudo-virtual channels and non-blocking writes

Disaggregated system domain

Global virtual address space consistency model

Dynamic update of the number of architected registers assigned to software threads using spill counts

Dynamic update of the number of architected registers assigned to software threads using spill counts

Locating node of named data elements in coordination namespace

Implementing modal selection of bimodal coherent accelerator

Implementing modal selection of bimodal coherent accelerator

Secure memory sharing

Relocation and persistence of named data elements in coordination namespace

Tracking transactions using extended memory features

Channel mechanisms for communicating with a processor event facility

I/O address translation method for specifying a relaxed ordering for I/O accesses

System for communicating command parameters between a processor and a memory flow controller

Access of named data elements in coordination namespace

Coordination namespace processing

Implementing modal selection of bimodal coherent accelerator

JOHNS CHARLES R

Design structure for performing cacheline polling utilizing store with reserve and load when reservation lost instructions

System and method for an isolated process to control address translation

Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling

Structure for performing cacheline polling utilizing a store and reserve instruction

Structure for a livelock resolution circuit

TOSHIBA KK

Systems and methods for thermal management

Systems and methods for thermal sensing

AGUILAR JR MAXIMINO

Virtual world event notifications from within a persistent world game

Configure offline player behavior within a persistent world game

EICHENBERGER ALEXANDRE E

Data parallel function call for determining if called routine is data parallel

Data parallel function call for determining if called routine is data parallel

D AMORA BRUCE D

Displaying images of conference call participants

FLACHS BRIAN

Arithmetic decoding acceleration

CHEN WEN-TZER T

Mechanisms for priority control in resource allocation