Inventor

DESAI JAYEN J

US9 patents

⚠️ This page may combine multiple inventors who share the name “DESAI JAYEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEWLETT PACKARD DEVELOPMENT CO

5 patents

US7610526B2Oct 27, 2009

On-chip circuitry for bus validation

HEWLETT PACKARD DEVELOPMENT CO22 citations91

US7498858B2Mar 3, 2009

Interpolator systems with linearity adjustments and related methods

HEWLETT PACKARD DEVELOPMENT CO9 citations80

US7276952B2Oct 2, 2007

Clock signal generation using digital frequency synthesizer

HEWLETT PACKARD DEVELOPMENT CO8 citations73

US6583650B2Jun 24, 2003

Latching annihilation based logic gate

HEWLETT PACKARD DEVELOPMENT CO0 citations51

US7391221B2Jun 24, 2008

On-die impedance calibration

HEWLETT PACKARD DEVELOPMENT CO0 citations38

FRANCOM ERIN D

2 patents

US9628092B2Apr 18, 2017

Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning

FRANCOM ERIN D4 citations65

US9178502B2Nov 3, 2015

Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning

FRANCOM ERIN D4 citations65

DESAI JAYEN J

1 patent

US9124257B2Sep 1, 2015

Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement

DESAI JAYEN J5 citations64

HEWLETT PACKARD CO

1 patent

US6459304B1Oct 1, 2002

Latching annihilation based logic gate

HEWLETT PACKARD CO3 citations62