Inventor

DORIS BRUCE

US47 patents

⚠️ This page may combine multiple inventors who share the name “DORIS BRUCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DORIS BRUCE

CHENG KANGGUO

Raised source/drain structure for enhanced strain coupling from stress liner

MOSFET with work function adjusted metal backgate

Raised source/drain structure for enhanced strain coupling from stress liner

MOSFET with recessed channel film and abrupt junctions

Integrated circuit with a thin body field effect transistor and capacitor

Integrated circuit with a thin body field effect transistor and capacitor

MOSFET with recessed channel film and abrupt junctions

Fully-depleted SON

Raised source/drain structure for enhanced strain coupling from stress liner

MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation

FET with self-aligned back gate

Structure and method to minimize regrowth and work function shift in high-k gate stacks

GLOBALFOUNDRIES INC

Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material

Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device

Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process

Methods of forming isolated germanium-containing fins for a FinFET semiconductor device

Method for single fin cuts using selective ion implants

Methods of modulating strain in PFET and NFET FinFET semiconductor devices

Methods of forming replacement fins for a FinFET device

Fin isolation structures facilitating different fin isolation schemes

Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material

Virtual relaxed substrate on edge-relaxed composite semiconductor pillars

Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask

IBM

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

FinFET device having a high germanium content fin structure and method of making same

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate

Integrated circuit with a thin body field effect transistor and capacitor

Methods of planarization

Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate

Fabrication of silicon germanium-on-insulator FinFET

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

Fabrication of silicon germanium-on-insulator finFET

ST MICROELECTRONICS INC

Silicon germanium-on-insulator FinFET

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

FinFET device having a high germanium content fin structure and method of making same

Method for the formation of a protective dual liner for a shallow trench isolation structure

Memory device having multiple dielectric gate stacks and related methods

Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods

BEDELL STEPHEN W

Strained silicon and strained silicon germanium on insulator

Strained silicon and strained silicon germanium on insulator field-effect transistor

COMMISSARIAT ENERGIE ATOMIQUE

Low leakage dual STI integrated circuit including FDSOI transistors

Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same

GLOBALFOUNDRIES US 2 LLC

Integrated circuit with a thin body field effect transistor and capacitor

LIU QING

Isolation regions for SOI devices