Inventor

JEONG DEOG-KYOON

KR129 patents

⚠️ This page may combine multiple inventors who share the name “JEONG DEOG-KYOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JEONG DEOG-KYOON

SILICON IMAGE INC

System and method for sending multiple data signals over a serial link

System and method for sending multiple data signals over a serial link

Multisection memory bank system

Wide frequency-range delay-locked loop circuit

Continuous-time, low-frequency-gain/high-frequency-boosting joint adaptation equalizer and method

Phase lock loop with coarse control loop having frequency lock detector and device including same

Wide range multi-phase delay-locked loop

Frequency comparator with hysteresis between locked and unlocked conditions

System and method for high-speed, synchronized data communication

Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies

High density column drivers for an active matrix display

Transition-controlled digital encoding and signal transmission system

Voltage-controlled oscillator resistant to supply voltage noise

Method and apparatus for data recovery in a digital data stream using data eye tracking

Skew-insensitive low voltage differential receiver

Power saving circuit and method for driving an active matrix display

High-speed and high-precision phase locked loop having phase detector with dynamic logic structure

System and method for driving columns of an active matrix display

DC-balanced and transition-controlled encoding method and apparatus

High-speed and high-precision phase locked loop having phase detector with dynamic logic structure

Communications architecture for transmission of data between memory bank caches and ports

Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization

Method and apparatus for bidirectional data transfer between a digital display and a computer

Dynamically biased full-swing operation amplifier for an active matrix liquid crystal display driver

CMOS driver and on-chip termination for gigabaud speed data communication

System and method for high-speed, synchronized data communication

GCT SEMICONDUCTOR INC

Single chip CMOS transmitter/receiver

Single chip CMOS transmitter/receiver

Mixer structure and method for using same

Phase lock loop (PLL) apparatus and method

Mixer structure and method of using same

Single chip CMOS transmitter/receiver and method of using same

Single chip CMOS transmitter/receiver and method of using same

Phase lock loop (PLL) apparatus and method

Gm-C tuning circuit with filter configuration

Gm-C tuning circuit with filter configuration

SUN MICROSYSTEMS INC

High speed serial link for fully duplexed data communication

System for Distributing Clocks

High speed serial link for fully duplexed data communication

High speed serial link for fully duplexed data communication

High speed serial link for fully duplexed data communication

SILICON IMAGE

Memory architecture with multiple serial communications ports

Method and system for nesting of communications packets

Method and system for communicating control information via out-of-band symbols

Method and system for host handling of communications errors

SAMSUNG ELECTRONICS CO LTD

Data receiving method and circuit of digital communication system

Method for generating digital communication system clock signals &amp; circuitry for performing that method

GLOBAL COMM TECHNOLOGY INC

VCO-mixer structure

JEONG DEOG KYOON

High speed serial link for fully duplexed data communication

DEOG KYOON JEOG

Clock generator

Method for generating digital communication system clock signals & circuitry for performing that method