Inventor

LAIS ERIC N

US56 patents

⚠️ This page may combine multiple inventors who share the name “LAIS ERIC N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAIS ERIC N

IBM

Directory tree multinode computer system

Synchronous input/output computer system including hardware invalidation of synchronous input/output context

Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages

Synchronous data input/output system using prefetched device table entry

Computer system including synchronous input/output and hardware assisted purge of address translation cache entries of synchronous input/output transactions

Error detection and recovery for synchronous input/output operations

Dynamic universal port mode assignment

Peripheral component interconnect express (PCIE) pseudo-virtual channels and non-blocking writes

Upbound input/output expansion request and response processing in a PCIe architecture

Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations

Synchronous input / output hardware acknowledgement of write completions

Synchronous input/output (I/O) cache line padding

Multi-packet processing with ordering rule enforcement

Dynamic universal port mode assignment

Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIE) environment

Translation of input/output addresses to memory addresses

Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations

Management of data transaction from I/O devices

Direct memory access (DMA) address translation with a consecutive count field

Direct memory access (DMA) address translation with a consecutive count field

Hazard queue for transaction pipeline

Input/output computer system including hardware assisted autopurge of cache entries associated with PCI address translations

Prefetch miss indicator for cache coherence directory misses on external caches

Transmission of a message based on a determined cognitive context

Configurable I/O address translation data structure

Configurable I/O address translation data structure

Management of data transaction from I/O devices

Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages

Maintaining cyclic redundancy check context in a synchronous I/O endpoint device cache system

Error detection and recovery for synchronous input/output operations

Translation of input/output addresses to memory addresses

Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment

Scalable I/O adapter function level error detection, isolation, and reporting

Multi-packet processing with ordering rule enforcement

LAIS ERIC N

Implementing PCI-express memory domains for single root virtualized devices

System and method for routing I/O expansion requests and responses in a PCIE architecture

Memory controller having tables mapping memory addresses to memory modules

Determination via an indexed structure of one or more partitionable endpoints affected by an I/O message

Selection of a domain of a configuration access

Interrupt source controller with scalable state structures

CRADDOCK DAVID

Translation of input/output addresses to memory addresses

Converting a message signaled interruption into an I/O adapter event notification

Runtime determination of translation formats for adapter functions

Converting a message signaled interruption into an I/O adapter event notification

Associating input/output device requests with memory associated with a logical partition

GREGG THOMAS A

Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment

Upbound input/output expansion request and response processing in a PCIe architecture

Non-standard I/O adapters in a standardized I/O architecture

BRICE JR FRANK W

Measurement facility for adapter functions

CRADDOCK DAVID F

Scalable I/O adapter function level error detection, isolation, and reporting