Inventor
KIM ILHYUN
KR20 patents
⚠️ This page may combine multiple inventors who share the name “KIM ILHYUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
APPLE INC
6 patentsUS12585469B2Mar 24, 2026
Trace cache access prediction and read enable
APPLE INC0 citations50
US12547409B2Feb 10, 2026
Trace cache that supports multiple different trace lengths
APPLE INC0 citations50
US12353882B1Jul 8, 2025
Next fetch prediction using history
APPLE INC0 citations50
US12265823B2Apr 1, 2025
Trace cache with filter for internal control transfer inclusion
APPLE INC0 citations50
US12373215B2Jul 29, 2025
Using a next fetch predictor circuit with short branches and return fetch groups
APPLE INC0 citations48
US12530193B2Jan 20, 2026
Trace cache techniques based on biased control transfer instructions
APPLE INC0 citations46
INTEL CORP
3 patentsUS10409612B2Sep 10, 2019
Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution
INTEL CORP7 citations82
US7925834B2Apr 12, 2011
Tracking temporal use associated with cache evictions
INTEL CORP5 citations54
US10409611B2Sep 10, 2019
Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution
INTEL CORP0 citations50
MARDEN MORRIS
3 patentsUS8521993B2Aug 27, 2013
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
MARDEN MORRIS4 citations59
US8438369B2May 7, 2013
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
MARDEN MORRIS4 citations59
US9524191B2Dec 20, 2016
Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements
MARDEN MORRIS1 citations48
RAPPOPORT LIHU
2 patentsUS8433850B2Apr 30, 2013
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
RAPPOPORT LIHU6 citations70
US8127085B2Feb 28, 2012
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
RAPPOPORT LIHU4 citations60