Inventor

SHAEFFER IAN P

US93 patents

⚠️ This page may combine multiple inventors who share the name “SHAEFFER IAN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAEFFER IAN P

RAMBUS INC

Integrated circuit heating to effect in-situ annealing

Memory controller with staggered request signal output

Integrated circuit with graduated on-die termination

Memory controller with staggered request signal output

Memory component with on-die termination

On-die termination control

On-die termination control

Controlling a flash device having time-multiplexed, on-die-terminated signaling interface

Variable-width memory module and buffer

Point-to-point connection topology for stacked devices

Strobe acquisition and tracking

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Error correction in a memory device

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Memory device with circuitry to transmit feedback indicative of a phase relationship

Deferred fractional memory row activation

Memory controller with staggered request signal output

Deferred fractional memory row activation

Memory controller with staggered request signal output

Memory with deferred fractional row activation

Clock generation for timing communications with ranks of memory devices

Memory controller with staggered request signal output

Memory with deferred fractional row activation

Memory with deferred fractional row activation

Clock generation for timing communications with ranks of memory devices

Strobe acquisition and tracking

Buffered memory module having multi-valued on-die termination

Reducing memory refresh exit time

Controlling memory devices that have on-die termination

Memory disturbance recovery mechanism

Nonvolatile memory device with time-multiplexed, on-die-terminated signaling interface

Command-triggered on-die termination

Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device

Memory controller that controls termination in a memory device

SHAEFFER IAN P

Memory controller with staggered request signal output

Integrated circuit with staggered signal output

Memory system for error detection and correction coverage

On-die termination of address and command signals

OH KYUNG SUK

Controlling on-die termination in a dynamic random access memory device

Dynamic on-die termination selection

Controlling dynamic selection of on-die termination

HEWLETT PACKARD DEVELOPMENT CO

Stencil device for accurately applying solder paste to a printed circuit board

Printed circuit board having solder bridges for electronically connecting conducting pads and method of fabricating solder bridges

STOTT BRET

Memory controller, system and method for read signal timing calibration

HEWLETT PACKARD CO

Connection block for interfacing a plurality of printed circuit boards

SUN MICROSYSTEMS INC

Method and apparatus for data capture on a bi-directional bus

HARRIS JAMES EDWARD

Memory with deferred fractional row activation

ZERBE JARED L

Clock generation for timing communications with ranks of memory devices