Inventor

NARAYANASWAMI RAVI

US47 patents

⚠️ This page may combine multiple inventors who share the name “NARAYANASWAMI RAVI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYANASWAMI RAVI

GOOGLE LLC

Neural network compute tile

Neural network accelerator with parameters resident on chip

Neural network instruction set architecture

Accessing data in multi-dimensional tensors using adders

Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Accessing prologue and epilogue data

Multi-input floating-point adder

Accessing data in multi-dimensional tensors using adders

Hardware double buffering using a special purpose computational unit

Exploiting input data sparsity in neural network compute units

Alternative loop limits for accessing data in multi-dimensional tensors

Accessing prologue and epilogue data

Matrix processing apparatus

Neural network instruction set architecture

Exploiting input data sparsity in neural network compute units

Neural network compute tile

Neural network instruction set architecture

Exploiting input data sparsity in neural network compute units

Hardware double buffering using a special purpose computational unit

Matrix processing apparatus

Virtualizing external memory as local to a machine learning accelerator

Image transformation for machine learning

Neural network compute tile

Neural network compute tile

Neural network accelerator with parameters resident on chip

Neural network accelerator with parameters resident on chip

Matrix processing apparatus

Hardware double buffering using a special purpose computational unit

Alternative loop limits for accessing data in multi-dimensional tensors

Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Neural network accelerator tile architecture with three-dimensional stacking

Virtualizing external memory as local to a machine learning accelerator

Image transformation for machine learning

Low-power adder circuit

Redistributing tensor elements between machine learning computing units

Preemption in a machine learning hardware accelerator

Low-power adder circuit

Multi-partition memory sharing with multiple components

GOOGLE INC

Neural network instruction set architecture

Neural network compute tile

Exploiting input data sparsity in neural network compute units

Neural network accelerator tile architecture with three-dimensional stacking

Matrix processing apparatus

Matrix processing apparatus

Matrix processing apparatus

Matrix processing apparatus

ZILOG INC

Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers