Inventor

WOO DONG HYUK

US58 patents

⚠️ This page may combine multiple inventors who share the name “WOO DONG HYUK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOO DONG HYUK

GOOGLE LLC

Neural network compute tile

Scheduling neural network processing

Permuting in a matrix-vector processor

Neural network accelerator with parameters resident on chip

Neural network instruction set architecture

Accessing data in multi-dimensional tensors using adders

Permuting in a matrix-vector processor

Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Accessing prologue and epilogue data

Accessing data in multi-dimensional tensors using adders

Hardware double buffering using a special purpose computational unit

Exploiting input data sparsity in neural network compute units

Alternative loop limits for accessing data in multi-dimensional tensors

Accessing data in multi-dimensional tensors

Accessing prologue and epilogue data

Matrix processing apparatus

Neural network instruction set architecture

Exploiting input data sparsity in neural network compute units

Neural network compute tile

Neural network instruction set architecture

Scheduling neural network processing

Exploiting input data sparsity in neural network compute units

Accessing data in multi-dimensional tensors

Permuting in a matrix-vector processor

Permuting in a matrix-vector processor

Permuting in a matrix-vector processor

Hardware double buffering using a special purpose computational unit

Matrix processing apparatus

Image transformation for machine learning

Scheduling neural network processing

Neural network compute tile

Permuting in a matrix-vector processor

Neural network compute tile

Permuting in a matrix-vector processor

Neural network accelerator with parameters resident on chip

Neural network accelerator with parameters resident on chip

Matrix processing apparatus

GOOGLE INC

Neural network instruction set architecture

Neural network compute tile

Exploiting input data sparsity in neural network compute units

Accessing data in multi-dimensional tensors

Accessing data in multi-dimensional tensors

Matrix processing apparatus

Matrix processing apparatus

Matrix processing apparatus

Matrix processing apparatus

INTEL CORP

Monitoring vector lane duty cycle for dynamic optimization

Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor

Collective communications apparatus and method for parallel systems

SEONG NAK HEE

Systems and methods providing wear leveling using dynamic randomization for non-volatile memory